Sampling Circuit Stray Capacitance Reduction

The patent divides the transistor structure into distinct regions with different metallizations. The source and drain regions are segmented with separate metallizations (first and second metallizations), and a third metallization is introduced between them. This segmentation allows different parts of the transistor to have different electrical characteristics, reducing stray capacitance between source and drain while maintaining signal integrity.

The third metallization acts as an intermediary element between the source and drain regions. By introducing this intermediate conductive layer and connecting it to a reference voltage, the patent creates a controlled electrical environment that reduces unwanted capacitance effects. The intermediary metallization serves as a buffer that prevents direct capacitive coupling between source and drain, thereby reducing signal attenuation and phase-shifting.

The patent combines the third metallization with existing source and drain metallization layers, forming an integrated structure. Rather than adding completely separate components, the invention merges the reference voltage connection into the existing transistor fabrication process. The first, second, and third metallizations are formed as part of the same metallization layer, allowing them to be manufactured together in a unified process flow.

The third metallization serves multiple functions: it provides a reference voltage connection, reduces stray capacitance between source and drain, and maintains signal integrity. By designing this single structural element to perform multiple functions, the patent avoids the need for additional separate components or processes, thereby improving signal accuracy without proportionally increasing manufacturing complexity.