Sampling Clock Circuit Dynamic Timing Adjustment
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Solution Overview
Problem
Existing communication circuits face difficulties in correctly sampling received data due to a fixed sampling clock timing, which can become out of sync with the data timing, especially when there is an error in start bit detection.
Innovation Solution
A communication circuit that generates a sampling clock signal with a frequency 'm' times greater than the bit rate, containing 'n' pulses in each bit period, and adjusts the timing based on majority operations to synchronize with the received data, using a sampling clock generating circuit, a majority circuit, and a communication control circuit to delay or advance the clock signal as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed sampling clock timing is used, then the circuit structure is simple, but the sampling accuracy deteriorates when timing synchronization errors occur
Solution Approach 1:
The patent implements dynamic sampling clock timing adjustment by detecting sampling errors and automatically advancing or delaying the sampling clock phase. The sampling clock generating circuit changes the sampling timing based on detected errors, transforming the fixed timing system into a dynamic one that adapts to synchronization requirements, thereby resolving the contradiction between simple circuit structure and high sampling accuracy.
Solution Approach 2:
The patent employs a feedback mechanism where the sampling error detection circuit monitors the sampling accuracy and provides feedback to the sampling clock generating circuit. Based on this feedback, the system automatically adjusts the sampling clock timing to correct synchronization errors, maintaining high sampling accuracy without requiring complex external intervention while preserving relatively simple circuit architecture.
2Ease of operation
If the sampling clock timing is fixed, then the circuit operation is simple, but the reliability of data reception deteriorates due to timing synchronization errors
Solution Approach 1:
The system dynamically adjusts the sampling clock timing based on detected synchronization errors, allowing the circuit to automatically adapt to timing drift without manual intervention. This dynamic operation maintains simple ease of use while significantly improving data reception reliability by correcting timing synchronization errors in real-time.
Solution Approach 2:
The sampling error detection and correction system operates autonomously, detecting its own timing synchronization errors and automatically correcting them by adjusting the sampling clock. This self-service capability ensures reliable data reception without requiring complex external control mechanisms, preserving ease of operation while enhancing reliability.
3Measurement precision
If multiple sampling points are used for majority voting, then the sampling accuracy improves, but the device complexity increases
Solution Approach 1:
The patent segments the sampling process into multiple discrete sampling points within each data period, taking multiple samples (e.g., 3 or 5 points) and applying majority voting to determine the correct data value. This segmentation approach improves sampling accuracy by reducing the impact of timing errors on any single sample while maintaining relatively simple circuit implementation through straightforward voting logic.
Solution Approach 2:
The system changes the sampling parameters by using multiple sampling points with different phases and applying majority voting. By varying the sampling phase parameters across multiple points and combining results through voting, the system achieves high sampling accuracy without requiring overly complex circuitry, as the voting mechanism can be implemented with simple logic circuits.
Data Source
AI summary
A communication circuit includes a sampling clock generating circuit generating a sampling clock signal having a frequency that is “m” times greater than a bit rate of the communication data and containing “n” pulses in each bit period of the communication data; and a sampling circuit sampling the communication data based on the sampling clock signal to obtain “n” sets of received data in each bit period of the communication data. The sampling clock generating circuit delays the sampling clock signal when a first one or more of the “n” sets of received data are different from a value of the rest of the “n” sets of received data, and advances the sampling clock signal when a value of a last one or more of the “n” sets of received data is different from a value of the rest of the “n” sets of received data.