Sampling Clock Error Calculation Circuit Using Correlation Offset
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Solution Overview
Problem
Asynchronous sampling clocks between a transmitter and a receiver lead to data errors due to unknown or changing sampling clock frequencies, especially in environments affected by production and operational factors.
Innovation Solution
A signal receiving circuit and method that calculates the error of the sampling clock by performing correlation operations on sample data groups with predetermined sequences, generating a sample data group offset, and adjusting the sampling clock frequency to synchronize the clocks, using a clock error calculation circuit and timing recovery circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the sampling clock frequency is set based on ideal conditions, then the system design is simple, but the sampling clock becomes asynchronous due to production and environmental factors, leading to data errors
Solution Approach 1:
The patent implements a feedback mechanism where the receiver calculates the sampling clock error by comparing correlation results of sample data groups with predetermined sequences, then feeds back this error information to adjust the sampling clock frequency, ensuring continuous synchronization despite production tolerances and environmental variations
Solution Approach 2:
The patent replaces mechanical/manual clock synchronization with an automated digital signal processing system that uses correlation operations and error calculation circuits to automatically detect and correct sampling clock frequency deviations, eliminating the need for manual adjustment and improving reliability
2Reliability
If the sampling clock frequency is adjusted to compensate for errors, then data accuracy is improved, but the system complexity increases due to additional error calculation and timing recovery circuits
Solution Approach 1:
The receiver performs self-diagnosis and self-correction by autonomously calculating the sampling clock error using correlation operations on received signal segments and automatically adjusting its own sampling clock frequency, eliminating the need for external synchronization equipment or manual intervention
Solution Approach 2:
The timing recovery circuit performs multiple functions including correlation operation, error calculation, and clock frequency adjustment within a single integrated system, reducing the need for separate dedicated circuits for each function and optimizing the balance between reliability and complexity
3Measurement precision
If correlation operations are performed on sample data groups with predetermined sequences, then the sampling clock error can be accurately calculated, but the processing time and computational complexity increase
Solution Approach 1:
The patent embeds predetermined sequences in advance within the signal structure (such as in pilot symbols or training sequences), allowing the receiver to perform correlation operations directly on these pre-placed sequences without requiring additional signal transmission or processing steps, thus achieving accurate error detection efficiently
Solution Approach 2:
The patent extracts specific predetermined sequences from the received signal for dedicated correlation operation, separating the error detection function from the main data processing stream and enabling efficient, focused computation on only the relevant signal portions for clock error calculation
Data Source
AI summary
A method for calculating an error of a sampling clock is provided. The sampling clock is used for sampling a signal to generate a first sample data group and a second sample data group. Each of the first and second sample data groups includes a header having a predetermined sequence. The method includes: performing a correlation operation on the first and second sample data groups with data of the predetermined format to obtain first and second correlation results, respectively; comparing the first and second correlation results to generate a sample data group offset; and generating the error of the sampling clock according to the sample data group offset and a time difference between the first and second sample data groups.