Sampling Clock Phase Adjustment for Jitter-Tolerant Data Recovery
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Solution Overview
Problem
Electronic circuits face challenges in maintaining accurate sampling timing due to data jitter, leading to increased bit errors, especially when jitter tolerance is low.
Innovation Solution
An electronic circuit is designed with a clock recovery circuit that generates reference clock signals based on reception data, a sampling clock generator that adjusts the phase of the sampling clock signal according to the jitter value, and a sampler that recovers data using the adjusted sampling clock, thereby improving jitter tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed sampling timing is used for data recovery, then the circuit operation is simple, but bit errors increase when data jitter occurs
Solution Approach 1:
The patent implements dynamic sampling timing adjustment by generating multiple sampling clock signals with different phases and selectively applying them based on detected jitter conditions. The sampling clock generator creates phase-varied clock signals, and the controller dynamically selects the appropriate phase to match the jittered data timing, thereby maintaining high data recovery accuracy under varying jitter conditions without oversimplifying the circuit.
Solution Approach 2:
The patent changes the phase parameter of the sampling clock signal dynamically. By detecting jitter in the received data and adjusting the phase of the sampling clock accordingly, the system adapts to timing variations in the incoming data stream. This parameter adjustment allows the sampler to accurately capture data bits even when their arrival times vary due to jitter, resolving the contradiction between reliability and complexity.
2Adaptability or versatility
If sampling timing is adjusted to compensate for jitter, then jitter tolerance improves, but the circuit complexity increases
Solution Approach 1:
The patent segments the sampling clock generation into multiple phase versions, each capable of handling different jitter conditions. Instead of using a single complex adjustable clock, the system divides the clock signal into several discrete phase options (e.g., early, nominal, late phases). The controller selects the appropriate segment based on jitter detection, providing high jitter tolerance through a manageable set of discrete options rather than continuous adjustment.
Solution Approach 2:
The patent implements partial adjustment by providing a limited set of phase options rather than continuous phase adjustment. The sampling clock generator creates multiple discrete phase versions (excessive action), and the controller selects the appropriate subset based on actual jitter conditions (partial action). This approach achieves sufficient jitter tolerance for practical applications without implementing a fully continuous and therefore more complex phase adjustment mechanism.
3Measurement precision
If multiple reference clock signals are generated based on different reception data, then sampling timing accuracy improves, but the processing complexity increases
Solution Approach 1:
The patent performs preliminary generation of multiple reference clock signals with different phases before the actual sampling process. The clock recovery circuit anticipates potential jitter conditions by pre-generating clock signals that cover a range of phase possibilities. This preliminary action allows the system to quickly select the appropriate reference clock without complex real-time calculation during sampling, improving timing accuracy while managing processing complexity through advance preparation.
Data Source
AI summary
An electronic circuit includes a clock recovery circuit that generates a first reference clock signal based on first reception data and generates a second reference clock signal based on second reception data received after the first reception, a sampling clock generator that generates a sampling clock signal having a phase based on a phase difference between the first reference clock signal and the second reference clock signal, and a sampler that recovers the second reception data based on the generated sampling clock signal.