Sampling Clock Offset Tracking in Multi-Carrier Systems

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional multi-carrier communication systems require significant computational resources to estimate and compensate for sampling clock offsets, leading to increased complexity and load on the receiver.

Innovation Solution

An apparatus and method that includes a compensating circuit to adjust phases of received symbols, a data removal circuit to isolate transmitted data, and a computing circuit to generate and adjust the sampling clock offset, reducing computational complexity and continuously compensating received symbols.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional sampling clock offset compensation is performed using multiple pilot symbols and complex computations, then sampling clock offset can be estimated and compensated, but the computational resources and complexity of the receiver increase significantly

Engineering Contradiction:
Improvesampling clock offset estimation accuracyVSAvoidreceiver computational complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts and removes the predetermined transmitted data from the compensated symbols to generate data removal symbols. This extraction process isolates the essential information needed for sampling clock offset estimation while eliminating unnecessary components, thereby reducing computational complexity without sacrificing estimation accuracy

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the parameter representation by using phase difference calculations and argument operations on the data removal symbols. Instead of performing complex conventional computations, the system transforms the problem into parameter-based calculations involving phase differences and angular measurements, which are computationally more efficient

Inventive Principle:
Principle #35Parameter changes

2Reliability

If conventional receiver processes are used to compensate sampling clock offset, then communication reliability is maintained, but the load on the computing unit increases

Engineering Contradiction:
Improvecommunication reliabilityVSAvoidcomputing unit processing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the compensation process into distinct functional blocks: a compensating circuit for phase adjustment, a data removal circuit for extracting transmitted data, and a computing circuit for offset calculation. This segmentation allows each circuit to perform its specific function efficiently, reducing the overall computational load while maintaining reliable compensation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a feedback mechanism where the computed sampling clock offset is used to adjust the sampling clock signal, and the process is repeated with updated compensating signals. This iterative feedback approach ensures reliable convergence to accurate offset values while distributing computational effort across multiple simpler iterations rather than one complex computation

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS7583740B2Apparatus and method for tracking sampling clock in multi-carrier communication system
Publication Date: 2009.09.01 REALTEK SEMICON CORP
  • US7583740B2 patent drawing
  • US7583740B2 patent drawing
  • US7583740B2 patent drawing

AI summary

An apparatus and method for tracking a sampling clock are disclosed. The apparatus includes a compensating circuit compensating phases of a first and a second received symbols according to a compensating signal and thereby generating a first and a second compensated symbols; a data removal circuit removing a first predetermined transmitted data from the first compensated symbol, and a second predetermined transmitted data from the second compensated symbol and thereby generating a first and a second data removal symbols; and a computing circuit generating a sampling clock offset according to the first and the second data removal symbols, and adjusting the sampling clock signal according to the sampling clock offset.