Sampling Clock Phase Detection for High-Speed Data Links
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Solution Overview
Problem
Conventional phase detection methods lose precision in high-speed data transmission, leading to circuit instability and performance degradation due to increased signal attenuation and bit rate, necessitating more accurate phase adjustments.
Innovation Solution
A phase detecting apparatus comprising a comparing unit, storage unit, and processing unit that generates and compares data sampling values and edge sampling values to determine phase adjustments of a sampling clock signal, using a phase adjusting control signal to stabilize the phase of the clock signal, especially in high-speed data transmission scenarios like USB 3.0 and PCIe Gen2.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional phase detection methods are used in high-speed data transmission, then data transmission bit rate can be increased, but phase adjustment precision deteriorates leading to circuit instability
Solution Approach 1:
The patent segments the sampling process into two distinct phases: data sampling (using first and second sampling clock signals) and edge sampling (using a third sampling clock signal). This segmentation allows the system to separately handle data value capture and transition detection, improving phase adjustment precision by focusing the edge sampling specifically on detecting phase transitions with higher accuracy despite high transmission speeds.
Solution Approach 2:
The patent performs preliminary edge sampling before final phase determination. By using the third sampling clock signal to sample at expected edge positions in advance, the system prepares edge sampling values that can be compared with data sampling values to detect phase transitions, enabling accurate phase adjustment even at high bit rates where signal attenuation is significant.
2Device complexity
If conventional phase detection uses only two adjacent data sampling values, then device complexity is reduced, but phase detection accuracy deteriorates under signal attenuation
Solution Approach 1:
The patent divides the sampling operation into multiple specialized sampling events: data sampling (capturing stable data values) and edge sampling (detecting transitions). This segmentation adds only one additional sampling clock signal and comparison operation while significantly improving accuracy by specifically targeting edge detection, which is critical for phase measurement in attenuated high-speed signals.
Solution Approach 2:
The patent introduces edge sampling values as an intermediary element between data sampling values and phase determination. These edge sampling values specifically capture transition information and serve as a mediator that enhances the accuracy of phase detection by providing dedicated edge information without requiring complex additional circuitry.
3Measurement precision
If more sampling points are used for phase detection, then phase adjustment precision is improved, but processing time increases
Solution Approach 1:
The patent segments sampling into focused data sampling and edge sampling operations that can be performed in parallel or alternating fashion. By dividing the sampling task into specialized operations rather than uniformly increasing sampling rate, the system achieves higher precision through targeted edge detection while maintaining processing efficiency through structured alternation of sampling phases.
Solution Approach 2:
The patent employs periodic alternation between data sampling and edge sampling phases, using different sampling clock signals in a structured sequence. This periodic action allows the system to accumulate precise phase information over multiple cycles while maintaining a predictable processing rhythm that prevents time loss despite the increased sampling complexity.
Data Source
AI summary
A phase detecting apparatus and a phase adjusting method are provided. Determine whether to output a phase adjusting control signal according to a first data sampling value, a second data sampling value and a third data sampling value that are successively generated, so as to adjust a phase of a sampling clock signal used to sample a data signal.