Sampling Clock Phase Adjustment for Jittered Disc Synchronization
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Solution Overview
Problem
Signal jitter causes the sampling clock in optical storage devices to sample analog signals at incorrect timings, leading to increased bit error rates and impaired synchronization and decoding of disc signals.
Innovation Solution
A method and apparatus that adjust the phase of the sampling clock by comparing sampled data with a synchronization pattern, generating statistical results to predict and correct the timing, thereby reducing the impact of jitter and improving signal decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signal jitter is present in the disc signal, then the sampling clock samples the analog signal at incorrect timings, but this causes the bit error rate to increase and synchronization to be impaired
Solution Approach 1:
The patent implements a feedback mechanism where the detected synchronization pattern timing information is fed back to adjust the sampling clock phase. The receiver continuously monitors the synchronization pattern position and dynamically adjusts the sampling clock to maintain optimal sampling timing, thereby resolving the contradiction between maintaining reliable synchronization and achieving precise sampling timing despite signal jitter.
Solution Approach 2:
The patent changes the phase parameter of the sampling clock based on detected synchronization pattern timing. By dynamically adjusting the sampling clock phase parameter according to the actual synchronization pattern position in the presence of jitter, the system maintains accurate sampling timing and resolves the contradiction between synchronization reliability and sampling precision.
2Reliability
If the sampling clock phase shifts due to signal jitter, then the sampling signal is determined as an incorrect signal level, but this impairs the decoding procedure of the disc signal
Solution Approach 1:
The patent performs preliminary detection of the synchronization pattern to determine the correct timing reference before proceeding with data decoding. By first identifying the synchronization pattern position and using it to establish the correct sampling timing, the system ensures that subsequent signal level detections and decoding operations are performed at the correct timing, thereby resolving the contradiction between decoding reliability and signal level detection accuracy.
Solution Approach 2:
The patent uses feedback from the synchronization pattern detection to continuously adjust the sampling clock phase. This feedback mechanism ensures that the sampling clock remains synchronized with the actual signal timing, preventing incorrect signal level determinations and maintaining high decoding accuracy despite the presence of signal jitter.
Data Source
AI summary
A detection apparatus of an optical storage device for detecting a synchronization signal includes a sampling module for sampling a disc signal to generate a plurality of sampled data, a comparing module coupled to the sampling module for comparing the sampled data and a synchronization pattern to generate a first compared result and to generate a second comparing result after a time interval, and an adjusting module coupled to the comparing module for gathering a statistic of the first and the second comparing results to generate an adjusting signal for adjusting a phase of the sampling clock.