Sampling Clock Phase Training With Fewer Receiver Sampling Circuits
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Solution Overview
Problem
Conventional receivers require multiple sampling clock signals with different phases, leading to increased chip area and production costs due to the need for numerous sampling circuits to determine the sampling phase accurately.
Innovation Solution
An electronic device with a clock generating circuit producing a sampling clock signal, a phase-early sampling clock signal, and a phase-late sampling clock signal, along with a training circuit that adjusts these signals in different time intervals to determine the optimal sampling phase using a reduced number of sampling circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple sampling clock signals with different phases are used to determine sampling phase accurately, then sampling accuracy is improved, but chip area and production costs increase due to needing numerous sampling circuits
Solution Approach 1:
The patent segments the sampling process into multiple time intervals, with each interval using a different sampling clock phase. Instead of having all sampling circuits operate simultaneously with different phases, the system sequentially activates sampling circuits with different phases across different time intervals. This temporal segmentation allows accurate phase determination while reducing the number of sampling circuits needed at any given moment, thereby reducing chip area.
Solution Approach 2:
The patent implements periodic action by cycling through different sampling clock phases in successive time intervals. The training circuit systematically varies the phase of sampling clock signals across multiple periods, allowing the receiver to determine the optimal sampling phase through periodic measurement cycles. This periodic approach enables accurate phase detection using a limited number of sampling circuits that are reused across different time intervals.
2Measurement precision
If multiple sampling clock signals with different phases are used to determine sampling phase accurately, then sampling accuracy is improved, but production costs increase
Solution Approach 1:
By segmenting the sampling process into time intervals with different phases, the patent reduces the total number of sampling circuits required. Fewer sampling circuits mean lower manufacturing costs while still achieving accurate sampling phase determination through the systematic variation of clock phases across time.
Solution Approach 2:
The periodic cycling through different phases allows the system to achieve comprehensive phase measurement accuracy using a smaller, more cost-effective set of sampling circuits. The same physical circuits are reused across different time intervals with different phase configurations, reducing production costs while maintaining measurement precision.
3Area of stationary object
If a reduced number of sampling circuits are used, then chip area and production costs are reduced, but sampling phase determination becomes more difficult
Solution Approach 1:
The patent introduces dynamic phase adjustment through the training circuit, which systematically varies the phase of sampling clock signals across different time intervals. This dynamic approach allows a small number of sampling circuits to effectively perform the work of many static circuits, as each circuit is tested under multiple phase conditions. The dynamic reconfiguration simplifies the overall device structure while maintaining determination accuracy.
Solution Approach 2:
The patent changes the phase parameter of the sampling clock signals dynamically across different time intervals. By varying this critical parameter systematically, the system enables accurate phase determination with fewer circuits. The parameter change approach transforms a spatial problem (needing many circuits) into a temporal problem (using fewer circuits over time), reducing device complexity.
Data Source
AI summary
An electronic device includes a clock generating circuit, a receiving circuit and a training circuit. The clock generating circuit generates a sampling clock signal, a phase-early sampling clock signal and a phase-late sampling clock signal. The receiving circuit samples received data according to the sampling clock signal, the phase-early sampling clock signal and the phase-late sampling clock signal to generate a sample result. The training circuit controls the clock generating circuit to generate the sampling clock signal and the corresponding phase-early sampling clock signal and phase-late sampling clock signal that have different phases in a plurality of different time intervals, respectively, to cause the receiving circuit to generate a plurality of sample results. The training circuit further determines a sampling phase of the sampling clock signal according to the sample results.