Sampling Clock Recovery for High-Bandwidth Nyquist-Rate Signals

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Solution Overview

Problem

Current clock synchronization methods, such as the Gardner algorithm and overhead-assisted synchronization, face challenges in high-bandwidth scenarios due to oversampling requirements and additional spectrum overheads, making it difficult to design filters and maintain optimal sampling moments.

Innovation Solution

A communication apparatus comprising a clock control circuit, a data sampling circuit, and a clock recovery circuit, which cooperatively adjust the sampling clock to lock it at an optimal sampling moment, thereby avoiding oversampling and maintaining accurate signal capture without increasing the complexity of the ADC or filter in high-bandwidth systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the Gardner algorithm is used for sampling clock recovery, then sampling clock synchronization can be achieved, but oversampling is required which limits application in high-bandwidth scenarios

Engineering Contradiction:
Improvesampling clock synchronization accuracyVSAvoidbandwidth efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent changes the fundamental parameter of sampling strategy from oversampling to Nyquist-rate sampling. By using a Nyquist filter followed by a latch circuit that captures the signal at the optimal moment within each sampling period, the system achieves clock synchronization without requiring oversampling, thereby improving bandwidth efficiency while maintaining synchronization accuracy.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If the overhead-assisted synchronization method is used, then sampling clock recovery can be performed, but additional spectrum overheads are caused and low bandwidth filter is required which increases design difficulty

Engineering Contradiction:
Improvesampling clock recovery accuracyVSAvoidfilter design complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts the clock synchronization function from the data path by using a dedicated latch circuit that operates independently. The latch circuit captures the filtered signal at the optimal moment without requiring separate overhead signals or complex narrowband filtering, thereby eliminating spectrum overheads and simplifying filter design while maintaining recovery accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

3Loss of information

If oversampling is performed to achieve accurate sampling, then information retention is improved, but ADC complexity increases

Engineering Contradiction:
Improvesignal information retentionVSAvoidADC complexity
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The patent performs preliminary filtering using a Nyquist filter before the ADC stage, which preconditions the analog signal to contain only the necessary frequency components. This allows the ADC to operate at the Nyquist rate without oversampling while still retaining all necessary signal information, thereby reducing ADC complexity while preventing information loss.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250202678A1Communication Apparatus and Signal Sampling Method
Publication Date: 2025.06.19 HUAWEI TECH CO LTD
  • US20250202678A1 patent drawing
  • US20250202678A1 patent drawing
  • US20250202678A1 patent drawing

AI summary

A communication apparatus includes a clock control circuit, a data sampling circuit, and a clock recovery circuit. The clock control circuit is configured to determine a sampling clock deviation of the data sampling circuit, and generate a first clock control signal based on the sampling clock deviation, where the first clock control signal is used to adjust a sampling clock of the data sampling circuit. The clock recovery circuit is configured to adjust the sampling clock of the data sampling circuit based on the first clock control signal, and send a clock signal to the data sampling circuit. The data sampling circuit is configured to sample an input analog signal based on the clock signal.