Sampling Device for CMOS Image Sensor Noise Reduction
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Solution Overview
Problem
CMOS image sensors face challenges in achieving low noise readout due to random telegraph signal (RTS) noise, particularly as device dimensions shrink, affecting the buffer's ability to sample voltage effectively.
Innovation Solution
The implementation of a sampling device with multiple sampling units and differential pair circuits that sample and process charge transfer and pixel reset voltages, employing capacitors and transistors to reduce noise through correlated double sampling (CDS) and sequential activation of sampling units to mitigate the impact of RTS noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If device dimension is shrunk to increase pixel density, then image sensor resolution is improved, but RTS noise increases due to buffer sampling issues
Solution Approach 1:
The sampling device is divided into multiple sampling units (first sampling unit, second sampling unit, third sampling unit, fourth sampling unit) that operate sequentially. Each sampling unit samples the column line voltage at different time points, allowing the system to capture multiple samples and perform noise reduction through differential processing, thereby resolving the RTS noise issue while maintaining high resolution
Solution Approach 2:
The patent implements preliminary sampling actions by capturing the column line voltage at multiple predetermined time points before final image processing. The first and second sampling units sample during the reset phase, while the third and fourth sampling units sample during the charge transfer phase, enabling pre-processing of noise reduction
2Measurement precision
If multiple sampling units are used to reduce noise, then signal-to-noise ratio is improved, but device complexity increases
Solution Approach 1:
Multiple sampling units are merged into a single integrated sampling device structure that shares common components such as the column line connection and control logic. The sampling units operate sequentially and their outputs are combined through differential processing, achieving noise reduction while minimizing the increase in device complexity through resource sharing
Data Source
AI summary
A device includes a current source and sampling units. Each of the sampling units includes a transistor and a capacitor electrically coupled to a gate of the transistor. The sampling units are sequentially activated such that the capacitor samples a voltage of a column line of a pixel array and are activated together such that the transistor is turned on according to the sampled voltage of the capacitor, to drain a current from the current source through an output node to generate an output voltage thereat.