Sampling Time-to-Digital MDLL for Spur-Reduced Phase Alignment
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Solution Overview
Problem
Multiplying delay-locked loops (MDLLs) experience significant noise and harmonic distortion due to spurs caused by replacing free-running edges with reference edges, as existing circuits lack fine resolution to accurately align phases, leading to perturbations in the output signal.
Innovation Solution
A sampling time-to-digital converter (STDC) is integrated into the feedback loop of the MDLL to generate a phase-error correction signal with sub-picosecond resolution, coupled with an edge generator to compare reference and free-running edges, providing both sign and magnitude of phase offset, allowing precise alignment and reducing spurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If reference edges are used to replace free-running edges in an MDLL, then phase alignment is achieved, but spurs and noise are generated due to perturbation of the output signal
Solution Approach 1:
The patent implements a feedback mechanism where the STDC continuously measures the phase offset between the delayed output signal and the reference signal, and adjusts the delay chain accordingly. This closed-loop feedback system enables precise phase alignment while minimizing spurs by making incremental adjustments rather than forced edge replacements.
Solution Approach 2:
The patent replaces the traditional mechanical edge-replacement mechanism with a digital time-to-digital conversion system. The STDC converts time delays into digital values that can be processed and adjusted without physical perturbation of the signal edges, thereby eliminating the spurs generated by mechanical edge replacement while maintaining phase alignment precision.
2Productivity
If existing phase detection circuits are used in MDLL, then basic phase comparison is achieved, but fine resolution is insufficient leading to inaccurate phase alignment
Solution Approach 1:
The patent transitions from traditional voltage-based phase detection to a time-domain measurement approach using the STDC. By measuring time delays directly in the time dimension rather than comparing voltages in the amplitude dimension, the system achieves sub-picosecond resolution that enables both fast convergence and accurate phase alignment.
Solution Approach 2:
The patent changes the measurement parameter from voltage level comparison to time delay measurement. The STDC measures the time difference between the reference signal and the delayed output signal, converting this time parameter into a digital control value that provides fine resolution for precise phase alignment while maintaining fast convergence.
3Object-affected harmful factors
If traditional loop filtering is used to reduce noise, then noise suppression is achieved, but power consumption increases
Solution Approach 1:
The patent replaces the analog loop filter with a digital processing approach using the STDC. The time-to-digital conversion and subsequent digital processing eliminate the need for power-consuming analog filtering circuitry while achieving equivalent or superior noise suppression through precise time measurement and digital control of the delay chain.
Data Source
AI summary
A multiplying delay-locked loop circuit includes a delay chain including a plurality of variable delay circuits connected in series and having a delay chain output, and a feedback loop including circuitry for deriving a digital control signal representing magnitude and sign of phase offset in the delay chain output, for controlling delay in ones of the variable delay circuits. The circuitry for deriving a digital control signal includes a sampling time-to-digital converter (STDC) configured to operate on a time delay between inputs to generate the digital control signal. The STDC subtracts a second difference the signals derived from the delay chain output and output of the feedback divider from a first difference between the signals derived from the delay chain output and output of the feedback divider to provide a difference value, and the difference value indicates sign and magnitude of output offset in the delay chain output.