Sampling Oscilloscope Timing Correction Using I/Q Reference Sampling
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Solution Overview
Problem
High-speed devices with increasing bit rates, such as 32 Gbps, require improved precision and reduced jitter error in sampling oscilloscopes to accurately measure signals, which existing technologies struggle to achieve effectively.
Innovation Solution
A sampling circuit that includes a trigger generation unit with a frequency synthesizer to generate a periodic signal detuned from a reference clock, a sampler driving unit for timing, and an error detection unit with samplers and a correction value calculation unit to correct time base errors, using both I and Q signals to improve time accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional sampling methods are used with direct digital synthesizer, then the system can operate, but the jitter error is large and time accuracy is insufficient for high-speed devices
Solution Approach 1:
The patent implements a feedback mechanism where the actual sampling timing is detected and compared with the ideal sampling timing, and the difference (timing error) is used to correct the time base for subsequent sampling operations. This closed-loop feedback system continuously reduces timing errors and jitter, improving measurement precision for high-speed devices.
Solution Approach 2:
The patent performs preliminary detection of the actual sampling timing before the main measurement process. By detecting the timing error in advance and correcting the time base beforehand, the system ensures that subsequent sampling operations occur at the optimal timing, preventing jitter accumulation.
2Measurement precision
If multiple samplers are added to improve time accuracy, then measurement precision improves, but device complexity and cost increase
Solution Approach 1:
The patent makes the existing sampler perform multiple functions: it simultaneously samples the signal to be measured and detects the actual sampling timing by sampling a reference signal (such as a clock signal or known pattern). This multi-functionality eliminates the need for separate detection samplers, reducing device complexity while maintaining high time accuracy.
Solution Approach 2:
The sampling system uses itself to detect timing errors. The same sampler that performs the main measurement function also samples a reference signal to detect timing deviations. This self-service approach eliminates the need for additional dedicated detection hardware, simplifying the overall system structure.
Data Source
AI summary
A frequency synthesizer 11a outputs a periodic signal r(t) at a frequency detuned by a predetermined frequency Δf [Hz] from a frequency of 1/integer of a frequency of a reference clock signal f0 synchronized with a signal to be measured ws. A first sampler unit 12 samples the signal to be measured ws at a timing of the trigger signal CLK. A second sampler unit 13a samples an I signal I(t) at the timing of the trigger signal CLK. A phase shifter 13b outputs a Q signal Q(t) obtained by shifting a phase of the reference clock signal f0 by 90°. A third sampler unit 13c samples the Q signal at the timing of the trigger signal CLK. A correction value calculation unit 13d calculates a correction value Δt(n) based on sampling data I(n) and Q(n) and a set value t(n) of a sampling time.