Sampling PLL Loop Bandwidth Control for Low-Noise Locking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Contemporary phase-locked loop (PLL) circuits in wireless communication networks face challenges in maintaining stability and tunability due to noise contributions from charge pumps and high phase detection gain, which can be exacerbated by process, voltage, and temperature variations.
Innovation Solution
A PLL design that incorporates a sampling circuit with a first switch, an integrator, and a voltage-controlled oscillator (VCO), where the sampling voltage is selectively sampled based on a feedback signal, integrated to generate a control voltage, and used to tune the VCO, with a feedback path controlling the switches to manage loop bandwidth and reduce noise susceptibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a charge pump is used in the PLL circuit, then frequency synthesis capability is improved, but noise susceptibility increases
Solution Approach 1:
The patent extracts and removes the charge pump component from the PLL circuit, replacing it with a sampling-based frequency synthesis approach. This eliminates the primary noise source while maintaining frequency synthesis functionality through alternative means (phase detector directly controlling the VCO via sampling capacitors).
Solution Approach 2:
The patent introduces sampling capacitors as intermediary elements between the phase detector and VCO. These capacitors sample the phase detector output at specific intervals, providing frequency synthesis control without the continuous current pumping action that generates noise in traditional charge pumps.
2Speed
If phase detection gain is increased to improve locking speed, then frequency acquisition speed is improved, but stability deteriorates due to noise amplification
Solution Approach 1:
The patent employs periodic sampling action instead of continuous high-gain amplification. The sampling capacitors periodically capture phase detector output voltage at controlled intervals, achieving frequency acquisition through time-domain sampling rather than amplitude-domain high-gain amplification, thus avoiding noise amplification while maintaining locking speed.
3Speed
If loop bandwidth is widened to improve tracking response, then frequency tracking speed is improved, but noise susceptibility increases
Solution Approach 1:
The patent implements dynamic loop bandwidth control through the sampling mechanism. The effective loop bandwidth adapts based on the sampling rate and timing, allowing fast tracking response when needed while naturally filtering out high-frequency noise through the periodic sampling action, thus achieving both speed and noise immunity.
Data Source
AI summary
Certain aspects of the present disclosure generally relate to methods and apparatus for generating oscillating signals. For example, certain aspects of the present disclosure provide a phase-locked loop (PLL) having a first switch coupled to a sampling input node of the PLL, an integrator coupled to an output of the sampling circuit, and a voltage-controlled oscillator (VCO) having an input coupled to an output of the integrator. In certain aspects, the PLL may also include a feedback path coupled to an output of the VCO and a control input of the first switch.