Hybrid Fractional-N Sampling PLL with DTC Calibration for Low Jitter
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Solution Overview
Problem
Conventional fractional-N sampling phase locked loops (PLLs) face challenges in generating low jitter clock signals due to component mismatches, leading to increased phase noise and jitter, particularly in high-data-rate applications like wireline and wireless communication systems.
Innovation Solution
A hybrid fractional-N sampling PLL with digital-to-time converter (DTC) calibration, where the output of a comparator is used in both the DTC calibration loop and as a control source for the integral input of the voltage-controlled oscillator, eliminating the need for a transconductance amplifier and its associated integrating capacitor, thus reducing potential offset mismatches and stabilizing the PLL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fractional-N sampling PLL uses transconductance amplifier and integrating capacitor for error cancellation, then phase locking function is achieved, but component mismatches increase phase noise and jitter
Solution Approach 1:
The patent extracts and removes the transconductance amplifier and integrating capacitor from the conventional PLL architecture. By replacing the analog error cancellation mechanism with a digital calibration approach using a lookup table, the invention eliminates the harmful analog components that are susceptible to mismatches, thereby reducing phase noise and jitter while maintaining phase locking functionality.
Solution Approach 2:
The patent substitutes the analog error cancellation mechanism (transconductance amplifier and integrating capacitor) with a digital calibration system. The digital-to-time converter uses a lookup table calibrated through a control loop to achieve error cancellation in the digital domain, replacing the vulnerable analog components with robust digital logic that is not susceptible to component mismatches.
2Manufacturing precision
If conventional fractional-N sampling PLL uses error cancellation techniques, then phase noise is reduced, but susceptibility to component mismatches increases
Solution Approach 1:
The patent replaces the analog error cancellation mechanism with a digital calibration system. The digital-to-time converter uses a lookup table that is calibrated through a control loop to achieve error cancellation in the digital domain, replacing the vulnerable analog components with robust digital logic that is not susceptible to component mismatches.
Solution Approach 2:
The patent creates a digital model of the timing errors through calibration and stores correction values in a lookup table. This digital copy of the error characteristics allows the system to compensate for phase errors without requiring precise analog component matching, as the correction is applied through digital timing adjustment rather than analog signal processing.
3Manufacturing precision
If hybrid fractional-N sampling PLL eliminates transconductance amplifier and integrating capacitor, then component mismatch is reduced, but device complexity changes
Solution Approach 1:
The patent extracts and removes the transconductance amplifier and integrating capacitor from the conventional PLL architecture. By replacing the analog error cancellation mechanism with a digital calibration approach using a lookup table, the invention eliminates the harmful analog components that are susceptible to mismatches, thereby reducing phase noise and jitter while maintaining phase locking functionality.
Solution Approach 2:
The patent changes the operational domain from analog to digital. The digital-to-time converter uses a lookup table calibrated through a control loop to achieve error cancellation in the digital domain, replacing the vulnerable analog components with robust digital logic. This parameter change from analog continuous signals to digital discrete values simplifies the circuit by eliminating sensitive analog components.
Data Source
AI summary
Presented herein are techniques for implementing a hybrid fractional-N sampling phase locked loop with accurate digital-to-time calibration. A method includes receiving, at a comparator, an output of a sampling phase detector of a phase locked loop, the output of the sampling phase detector of the phase locked loop also being supplied as a control source for a proportional control input of a voltage-controlled oscillator, supplying an output of the comparator as an input signal to a calibration loop of a digital-to-time converter, supplying an output of the digital-to-time converter to an input of the sampling phase detector, and supplying the output of the comparator as a control source for an integral control input of the voltage-controlled oscillator.