Sampling PLL Circuit for Fast Wake-Up With Lower Power
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Solution Overview
Problem
Conventional phase-locked loops (PLLs) consume excessive power in power-limited surveillance applications due to their always-on design, failing to phase lock quickly enough to conserve energy.
Innovation Solution
A phase-locked loop design incorporating a voltage-controlled oscillator, phase detector, loop filter, switch, and sampling circuit, which allows for selective enablement and disablement to conserve power, using a switchable sampling circuit to generate a digital code for the control signal and enabling components only when necessary for phase locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conventional PLL is designed to be always on, then the phase locking function is continuously available, but the power consumption increases excessively
Solution Approach 1:
The PLL system transitions from a static always-on design to a dynamic design where components can be enabled or disabled based on operational needs. The phase detector and loop filter are selectively enabled only when phase locking is required, allowing the system to adapt its power consumption state to match the actual surveillance application requirements.
Solution Approach 2:
The PLL components operate periodically rather than continuously. The phase detector and loop filter are activated only during periods when phase locking is needed (such as when motion is detected), and remain disabled during idle periods, creating a periodic on-off operation pattern that reduces average power consumption.
2Use of energy by moving object
If the PLL is disabled to save power, then the power consumption decreases, but the phase locking speed becomes insufficient when reactivated
Solution Approach 1:
The system performs preliminary actions by pre-charging capacitors and preparing the voltage-controlled oscillator before full PLL operation is required. When the phase detector and loop filter are enabled, the VCO is already in a ready state with charged capacitors, allowing the PLL to achieve phase locking quickly without requiring a long startup period.
Solution Approach 2:
The sampling circuit automatically captures and stores the control signal voltage across the loop filter capacitor when the PLL is disabled. This stored voltage serves the system by providing a ready-to-use initial state for the VCO, enabling fast reactivation without external intervention or complex reset circuits.
3Speed
If the sampling circuit captures the control signal, then the quick reactivation is enabled, but the circuit complexity increases
Solution Approach 1:
The sampling circuit functionality is merged with the existing switch that controls the VCO enablement. The same switch that enables/disables the VCO also triggers the sampling operation, eliminating the need for a separate sampling trigger circuit and reducing overall system complexity while maintaining fast reactivation capability.
Data Source
AI summary
A phase-locked loop (PLL) includes a voltage-controlled oscillator (VCO) that generates a PLL output signal having an oscillation frequency controlled by a control signal; a phase detector that generates a phase signal representing a difference in phase between the PLL output signal and a reference signal; a loop filter coupled to receive the phase signal; a switch; and a sampling circuit switchably coupled to receive the control signal of the VCO via the switch, and generating a code representing the control signal.