Sampling PLL Main-Loop Locking for Wide Lock Range
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Solution Overview
Problem
Current phase-locked loop (PLL) devices face challenges in achieving fast frequency and jitter specifications required for 5G communication, particularly due to a narrow lock range in sampling PLLs, which necessitates the addition of a frequency locking loop, increasing manufacturing costs and reducing integration reliability.
Innovation Solution
A phase-locked loop device that omits the frequency locking loop by using a voltage controlled oscillator, divider, sampling phase frequency detector, transconductance circuit, and loop filter to achieve phase locking solely with a main loop, where the sampling phase frequency detector samples a voltage based on phase division signals and applies either a supply voltage to a hold node to synchronize the reference clock signal with the output clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a sampling PLL is used to achieve fast frequency and jitter specifications, then the frequency and jitter performance is improved, but the lock range becomes narrow making it difficult to stably achieve phase lock
Solution Approach 1:
The patent implements a dual-loop architecture where a frequency locking loop dynamically adjusts the operating point of the voltage-controlled oscillator to keep it within the linear region, while the main phase-locked loop dynamically tracks phase differences. This dynamic coordination between the two loops enables both fast frequency response and stable phase locking across a wide range.
Solution Approach 2:
The frequency locking loop acts as an intermediary mechanism that preprocesses the frequency control by adjusting the VCO's operating point before the main phase-locked loop operates. This intermediary frequency locking function enables the main loop to focus on phase tracking with improved stability and extended lock range.
2Reliability
If a frequency locking loop is added to the sampling PLL to secure a fixed range, then the phase lock stability is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the frequency locking function and phase-locked loop function into a coordinated dual-loop system where both loops work together synergistically. The frequency locking loop and main phase-locked loop are integrated through shared components like the VCO and phase detector, reducing overall system complexity while maintaining enhanced performance.
Solution Approach 2:
The voltage-controlled oscillator serves multiple functions: it is controlled by both the frequency locking loop for operating point adjustment and the main phase-locked loop for phase tracking. This multi-functionality reduces the need for separate dedicated components, thereby reducing device complexity and manufacturing cost.
3Adaptability or versatility
If a frequency locking loop is added to extend the lock range, then the adaptability is improved, but the manufacturing cost increases
Solution Approach 1:
The patent segments the frequency control function into two parts: coarse frequency adjustment through the frequency locking loop and fine frequency/phase adjustment through the main phase-locked loop. This segmentation allows each loop to operate optimally within its designated range, extending the overall lock range while using standard, cost-effective components.
Solution Approach 2:
The dual-loop architecture ensures continuous frequency and phase control across a wide range by seamlessly coordinating the frequency locking loop and main phase-locked loop. This continuous operation without discontinuities or mode switching enables extended lock range while maintaining manufacturing efficiency through unified control architecture.
Data Source
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AI summary
A phase-locked loop device and its operating method are provided. The phase-locked loop device includes a voltage controlled oscillator configured to generate an output clock signal, a divider configured to divide the output clock signal into first and second phase division signals having a constant phase difference, a sampling phase frequency detector configured to sample a sampling voltage based on the first phase division signal and output any one of the sampling voltage, a first supply voltage, and a second supply voltage based on the second phase division signal, a transconductance circuit configured to output a conversion current based on a hold voltage, and a loop filter configured to generate a voltage control signal based on the conversion current and output the voltage control signal to the voltage controlled oscillator.