Sampling Phase Detector PLL for Low-Jitter, Low-Power Locking
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Solution Overview
Problem
The in-band jitter contribution of phase-locked loops (PLLs) is dominated by phase detector and charge pump noise, and increasing charge pump current to enhance effective gain results in higher power consumption and output noise, with limitations in scaled processes due to saturation margin constraints.
Innovation Solution
A phase-locked loop (PLL) circuit with a sampling phase detector that operates on a frequency-divided output of the voltage controlled oscillator (VCO), utilizing a transconductance cell for voltage-to-current conversion and a pulser circuit to control gain, thereby increasing the effective gain without increasing charge pump current, reducing power consumption and improving jitter performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge pump current is increased to enhance effective gain, then phase detector and charge pump noise is reduced, but power consumption and output noise increase
Solution Approach 1:
The patent changes the operating parameters by using a sampling phase detector that operates on a frequency-divided output of the VCO rather than the full-frequency output. This parameter change allows the system to achieve the same phase detection function at a lower effective frequency, reducing the required charge pump current and thereby reducing power consumption while maintaining jitter performance.
Solution Approach 2:
The patent introduces a frequency divider as an intermediary component between the VCO and the sampling phase detector. This intermediary divides the VCO output frequency before it reaches the phase detector, allowing the phase detection to occur at a lower frequency where less charge pump current is required, thus resolving the contradiction between jitter performance and power consumption.
2Reliability
If charge pump current is increased to enhance effective gain, then phase detector and charge pump noise is reduced, but output noise increases
Solution Approach 1:
By changing the operating frequency parameter through the frequency divider and sampling phase detector architecture, the system achieves effective phase detection at a reduced frequency. This parameter change allows for lower charge pump current operation, which simultaneously reduces both the in-band noise and the output noise, resolving the contradiction between jitter performance and output noise.
3Reliability
If charge pump current is increased, then effective gain is increased, but saturation margin limits are exceeded in scaled processes
Solution Approach 1:
The patent changes the frequency parameter of operation by using a frequency divider and sampling phase detector, which allows the phase detection to occur at a lower frequency. This parameter change enables the charge pump to operate with lower current while maintaining the same effective gain, thereby staying within the saturation margin limits of current sources in scaled semiconductor processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the locking range while reducing power consumption and improving jitter performance, offering a 6 decibel phase noise improvement without increasing output noise, and allows for fractional synthesis without complex digital-to-time converter circuits.
Implementation Method 1
utilizing a transconductance cell for voltage-to-current conversion
Data Source
Figure 1
Figure 2~3
Figure 4
AI summary
An example a phase-locked loop (PLL) circuit (100) includes a sampling phase detector (103) configured to receive a reference clock and a feedback clock and configured to supply a first control current and a pulse signal. The PLL further includes a charge pump (107) configured to generate a second control current based on the first control current and the pulse signal. The PLL further includes a loop filter (109) configured to filter the second control current and generate an oscillator control voltage. The PLL further includes a voltage controlled oscillator (VCO) (1 16) configured to generate an output clock based on the oscillator control voltage. The PLL further includes a frequency divider (118) configured to generate the reference clock from the output clock.