Sampling PLL Charge Pump Pulse Width Control for Low-Noise Stability

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Solution Overview

Problem

Conventional sampling phase detectors in phase-locked loops face limitations such as high detection gain, which requires sacrificing performance or using large external loop filters, preventing full integration on a chip and leading to increased noise and instability.

Innovation Solution

A sampling phase detector and charge pump with pulse width control, where the charge pump output current is controlled by a pulser circuit to adjust the duty cycle, allowing for selective gain adjustment without altering the oscillator signal or voltage-to-current converter gain, enabling full integration and reduced noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a sampling phase detector with large detection gain is used, then phase detection sensitivity is improved, but loop stability deteriorates and requires large external loop filters that prevent full integration

Engineering Contradiction:
Improvephase detection sensitivityVSAvoidloop stability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The charge pump operates dynamically with pulsed current output controlled by a pulser circuit. The current pump generates current pulses whose width is controlled by the reference signal, creating a dynamic response that adjusts to phase errors while maintaining stability through controlled timing rather than relying solely on high detection gain.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the operational parameters of the charge pump by controlling current pulse width rather than using continuous high gain. The pulser circuit adjusts the duty cycle of current pulses, transforming the charge pump from a static high-gain element into a dynamically controllable component that achieves stability through parameter modulation.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If large external loop filters are used to ensure loop stability, then stability is improved, but device complexity and integration difficulty increase

Engineering Contradiction:
Improveloop stabilityVSAvoidintegration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention extracts the stability control function from the external loop filter and embeds it within the charge pump circuitry itself. By incorporating the pulser circuit and duty cycle control directly into the charge pump, the system eliminates the need for large external loop filters, allowing full integration on a single chip while maintaining loop stability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The pulser circuit is merged with the charge pump to form an integrated unit. The combination of the current pump, pulser circuit, and duty cycle control creates a unified charge pump assembly that provides both phase-to-frequency conversion and stability control in a single integrated block, eliminating external components.

Inventive Principle:
Principle #5Merging (Combining)

3Power

If the charge pump output current is increased to improve response, then detection gain is improved, but noise and spurious signals increase

Engineering Contradiction:
Improvecharge pump output currentVSAvoidnoise and spurious signals
Core Design Contradiction:
PowerVSObject-generated harmful factors

Solution Approach 1:

The charge pump uses periodic pulsed current output instead of continuous current. The pulser circuit generates current pulses synchronized with the reference signal, creating periodic action that maintains detection gain while reducing noise. The pulsed nature allows precise timing control that minimizes spurious signals through coherent integration with the reference clock.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS7737743B1Phase-locked loop including sampling phase detector and charge pump with pulse width control
Publication Date: 2010.06.15 NAT SEMICON CORP
  • US7737743B1 patent drawing
  • US7737743B1 patent drawing
  • US7737743B1 patent drawing

AI summary

Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.