Sampling PLL Ripple Feedback for Fractional-N Spur Suppression
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Solution Overview
Problem
Phase-locked loops (PLLs) face challenges in providing a stable clock output due to phase jumps in the sampling clock, leading to spurs in the output clock spectrum, which existing solutions like narrow bandwidth filters, digital-to-time converters, phase dithering, and dual Control Digital-to-Analog Converter (CDAC) modules either compromise noise, power, or require complex calibration and matching.
Innovation Solution
A sampling PLL architecture using a single digital-to-analog converter (DAC) with a ripple integrator for negative feedback to adjust the compensation amplitude, eliminating spurs in the VCO control signal without the need for dual DACs or complex calibration, thereby simplifying control logic and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a narrow bandwidth low pass filter is used to remove ripple and smooth the VCO control signal, then the spurs are reduced, but the capture response time becomes long and stability issues arise
Solution Approach 1:
The patent implements a feedback mechanism where the ripple detector monitors the VCO control signal for ripple content and generates a compensation signal that is fed back to cancel the ripple. This active feedback approach removes spurs without requiring a narrow bandwidth filter, thus maintaining fast capture response time and stability.
Solution Approach 2:
The patent extracts and separately processes the ripple component from the VCO control signal using a ripple detector. By isolating the harmful ripple content and processing it through a dedicated compensation path, the system can remove spurs without affecting the main control signal path and its rapid response characteristics.
2Object-generated harmful factors
If a Digital to Time Converter (DTC) is used to adjust the phase of the reference clock, then the spurs are cancelled, but the linearity is difficult to achieve and calibration is required
Solution Approach 1:
The patent uses a feedback-based ripple cancellation approach where the ripple detector monitors the actual ripple in the VCO control signal and generates a compensation signal accordingly. This eliminates the need for complex pre-calibration of DTC components, as the system automatically adapts to the actual ripple conditions through feedback.
Solution Approach 2:
The ripple detector and compensation circuitry automatically detect and cancel their own generated ripple without requiring external calibration or matching. The system self-adjusts by monitoring its own output and generating the appropriate compensation signal, eliminating the need for complex calibration procedures.
3Object-generated harmful factors
If phase dithering is used to mitigate the spur, then the spurs are reduced, but the noise floor is raised and the control becomes complex
Solution Approach 1:
The patent employs a feedback mechanism that directly targets and cancels the ripple causing spurs, rather than using phase dithering which spreads the spur energy across a wider bandwidth. This selective cancellation approach reduces spurs without raising the noise floor, as it only affects the specific ripple frequency components.
Solution Approach 2:
The patent converts the harmful ripple effect into a useful signal by detecting the ripple and using it to generate a compensation signal. The detected ripple becomes the basis for creating the exact opposite signal needed to cancel it, transforming the harmful effect into a beneficial cancellation mechanism.
4Object-generated harmful factors
If dual CDAC modules are used to generate the control signal, then the spurs are reduced, but the complexity of control logic increases and power consumption rises
Solution Approach 1:
The patent merges the ripple detection and compensation functions into a single integrated circuit path that operates in conjunction with the existing single CDAC. By combining these functions rather than using dual CDAC modules, the system reduces power consumption while still achieving spur cancellation through the integrated ripple compensation mechanism.
Solution Approach 2:
The patent introduces a ripple detector as an intermediary component that monitors the VCO control signal and generates a compensation signal. This intermediary approach allows spur cancellation without requiring dual CDAC modules, thereby reducing power consumption while maintaining the necessary control functionality through the intermediary compensation path.
Data Source
AI summary
Embodiments herein relate to a sampling phase-locked loop (PLL) with a compensation circuit for reducing ripples due to the use of a fractional N divider. The compensation circuit includes a ripple amplifier and a ripple divider. The ripple amplifier receives an output voltage, Vmain, of a main sampling circuit of the PLL and amplifies its alternating current (AC) components. The amplified output voltage is provided to a ripple integrator which samples the minimum and maximum values to provide inputs to an operational amplifier (op amp). An output of the op amp is fed back to a digital-to-analog converter (DAC), which provides a corresponding compensation voltage, Vcomp. Vcomp is added to Vmain to provide a final output control voltage, Vctrl, to control a voltage-controlled oscillator (VCO) of the PLL.