Sampling PLL Circuit for Wide Lock Range and Stable Phase Lock
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Solution Overview
Problem
Existing phase-locked loops (PLLs) face challenges in achieving fast frequency and jitter specifications required by 5G standards, particularly with sampling PLLs having a narrow lock range and difficulties in integration due to the addition of separate frequency locking loops.
Innovation Solution
A phase-locked loop device utilizing a main loop with a voltage-controlled oscillator, divider, sampling phase frequency detector, transconductance circuit, charge pump, and loop filter, which secures a wide fixation range and proportional gain without additional loops, enabling stable phase lock and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a sampling PLL is used to achieve fast frequency and jitter specifications, then the frequency and jitter performance is improved, but the lock range becomes narrow making stable phase lock difficult
Solution Approach 1:
The patent combines the frequency detection function and phase detection function into a single sampling phase frequency detector. This merged detector outputs both a frequency detection signal (indicating whether frequency lock is achieved) and a phase detection signal (indicating phase difference), allowing the system to achieve wide lock range through frequency detection while maintaining phase lock stability through phase detection, resolving the contradiction between fast frequency response and stable phase locking.
2Adaptability or versatility
If a separate frequency locking loop is added to secure a fixed range, then the lock range is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the frequency detection and phase detection functions into one sampling phase frequency detector, eliminating the need for a separate frequency locking loop. The detector uses sampling at a specific phase to simultaneously determine both frequency lock status (via frequency detection signal) and phase difference (via phase detection signal), achieving wide lock range without increasing device complexity.
Solution Approach 2:
The sampling phase frequency detector serves multiple functions: it detects frequency differences to determine lock range, detects phase differences for phase locking, and generates both frequency detection signals and phase detection signals. This multi-functional design achieves wide lock range and stable phase locking without requiring additional dedicated circuits, reducing overall device complexity.
3Adaptability or versatility
If a separate frequency locking loop is added to secure a fixed range, then the lock range is improved, but integration difficulty increases
Solution Approach 1:
The patent integrates frequency detection and phase detection functions into a single sampling phase frequency detector circuit, eliminating the need for a separate frequency locking loop. This consolidation reduces the number of components and interconnections required, making the system easier to manufacture and integrate while achieving the desired wide lock range.
Data Source
AI summary
A phase-locked loop device and a method for operating the same, including: a voltage-controlled oscillator configured to generate an output clock signal; a divider configured to divide the output clock signal into a first phase division signal; a sampling phase frequency detector configured to: receive a first supply voltage, a second supply voltage different from the first supply voltage, and the first phase division signal, and based on determining that a phase difference between the first phase division signal and a reference clock signal corresponds to a first interval, output a hold voltage and a status signal for the phase difference; a transconductance circuit configured to output a first conversion current based on the hold voltage; a charge pump configured to output a second conversion current based on the status signal; and a loop filter configured to provide a voltage control signal to the voltage-controlled oscillator.


