Sampling Switch Circuit With Potential Divider for Higher ADC Bandwidth
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Solution Overview
Problem
Current sampling switch circuits, particularly in high-frequency applications like 5G, face limitations due to large capacitors, high transistor counts, and intrinsic delays, which hinder their maximum frequency operation and lead to harmonic distortion and reduced dynamic range in ADCs.
Innovation Solution
A sampling switch circuit design that eliminates the need for a bulky capacitor by using a potential divider circuit to provide a track-control voltage signal, reducing transistor count and parasitic capacitance, and controlling switch states with a clock signal to enhance tracking time constants and sampling frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a bootstrapping circuit with a large capacitor is used to provide constant gate-source voltage, then the on-resistance variation is minimized, but the maximum sampling frequency is reduced due to large time constants
Solution Approach 1:
The patent changes the voltage level parameter by applying a boosted gate voltage (VDD + VIN) instead of the conventional constant voltage (VDD). This parameter change allows the sampling switch to operate with lower on-resistance variation while reducing the time constant, thereby enabling higher sampling frequencies without requiring large capacitors
Solution Approach 2:
The patent applies preliminary action by pre-charging the gate capacitor to VDD + VIN before the sampling phase. This preliminary voltage preparation ensures that when the sampling switch turns on, the gate-source voltage is already optimized, eliminating the need for large capacitors to maintain voltage stability during sampling
2Reliability
If a bootstrapping circuit with multiple transistors is used to control the sampling switch, then the gate-source voltage can be maintained, but the transistor count and parasitic capacitance increase
Solution Approach 1:
The patent extracts and removes the bulky capacitor from the conventional bootstrapping circuit. By taking out this component, the circuit achieves simpler structure with fewer transistors and reduced parasitic capacitance, while still maintaining reliable gate-source voltage control through the alternative boosting mechanism
Solution Approach 2:
Instead of using a capacitor to store and maintain gate-source voltage (conventional approach), the patent inverts the approach by using an active voltage boosting circuit that dynamically generates the required voltage. This inversion eliminates the need for large capacitors and reduces the overall transistor count
3Device complexity
If a conventional sampling switch circuit is used, then the circuit structure is simple, but the tracking time constant is large which limits the sampling frequency
Solution Approach 1:
The patent changes the gate voltage parameter from VDD to VDD + VIN, which directly reduces the tracking time constant. This parameter change allows the circuit to maintain simplicity while achieving faster tracking and higher sampling frequencies, as the enhanced gate-source voltage improves the switching speed without adding circuit complexity
Data Source
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Figure 4A~4B
AI summary
A sampling switch circuit, comprising: an input node, connected to receive an input voltage signal to be sampled; a sampling transistor comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node; a potential divider circuit connected to the input node and a track-control node to provide a track-control voltage signal dependent on the input voltage signal at the track-control node; a hold-control node connected to receive a hold-control voltage signal; an output node connected to the drain terminal of the sampling transistor; and switching circuitry configured to connect the gate terminal of the sampling transistor to the track-control node or to the hold-control node in dependence upon a clock signal.