Low-Leakage Sampling Switch With Backgate Pre-Bias Control
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Solution Overview
Problem
Conventional low leakage switches in sample and hold systems suffer from significant leakage currents, especially at elevated temperatures, which affect charge preservation on sampling capacitors, leading to errors in reference current or voltage circuits, and increasing capacitance values to mitigate this issue results in larger, more power-consuming capacitors.
Innovation Solution
A low leakage switch design incorporating a pre-sampling stage with a pre-sampling transistor and capacitor, coupled with backgate voltage sampling capacitors, and a decoupling transistor to stabilize backgate voltages, reducing leakage currents by minimizing voltage differences across transistors and using differential amplifiers to further stabilize voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capacitance value of the sampling capacitor is increased to overcome leakage current effects, then charge preservation is improved, but the chip area and power consumption increase
Solution Approach 1:
The patent applies preliminary action by pre-charging the sampling capacitor to the input voltage level before the sampling switch opens. This is achieved by closing the sampling switch earlier or keeping it closed for a longer duration during the sampling phase, ensuring the capacitor is fully charged before the hold phase begins. This preliminary charging action eliminates the need for larger capacitance values to compensate for leakage effects.
2Reliability
If the capacitance value of the sampling capacitor is increased to overcome leakage current effects, then charge preservation is improved, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-charging the sampling capacitor to the input voltage level before the sampling switch opens. This is achieved by closing the sampling switch earlier or keeping it closed for a longer duration during the sampling phase, ensuring the capacitor is fully charged before the hold phase begins. This preliminary charging action eliminates the need for larger capacitance values to compensate for leakage effects.
3Measurement precision
If the hold time is extended to preserve the sampled voltage, then sampling accuracy is improved, but leakage current effects worsen
Solution Approach 1:
The patent applies preliminary action by pre-charging the sampling capacitor to the input voltage level before the sampling switch opens. This is achieved by closing the sampling switch earlier or keeping it closed for a longer duration during the sampling phase, ensuring the capacitor is fully charged before the hold phase begins. This preliminary charging action eliminates the need for larger capacitance values to compensate for leakage effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution significantly reduces leakage currents, allowing for longer hold times and reduced power consumption by maintaining stable backgate voltages and minimizing voltage errors on sampling capacitors, while enabling smaller capacitance values and reduced chip area.
Implementation Method 1
A low leakage switch design incorporating a pre-sampling stage with a pre-sampling transistor and capacitor
Implementation Method 2
a decoupling transistor to stabilize backgate voltages, reducing leakage currents by minimizing voltage differences across transistors
Data Source
AI summary
The invention relates to a low leakage switch having an input node for receiving an input voltage and an output node for providing an output voltage. The low leakage switch comprises a main sampling transistor the backgate voltage of which is biased through other transistors, and wherein the control gate of the main sampling transistor is controlled through a second control signal and the control gates of the other transistors are controlled through a first control signal, wherein the electronic device is further configured to activate the other transistor for adjusting the backgate voltage of the main sampling transistor through the first control signal before activating the main sampling transistor for sampling the input voltage on a main sampling capacitor through the second control signal.