Sampling Switch Circuit Without Bootstrap Capacitor Delay
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Solution Overview
Problem
Current sampling switch circuits, particularly those using bootstrapping techniques, face limitations at high sampling frequencies due to large capacitors, high transistor counts, and intrinsic delays, which hinder their performance in applications requiring high speed and resolution, such as 5G technology.
Innovation Solution
A sampling switch circuit design that eliminates the need for a bulky capacitor by using a potential divider circuit to generate a track-control voltage signal based on the input voltage, reducing the transistor count and parasitic capacitance, and controlling the sampling transistor states with a clock signal, thereby enhancing the tracking time constant and reducing on-resistance variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a bootstrapping circuit with a large capacitor is used to provide constant gate-source voltage, then on-resistance variations are minimized, but the maximum operation frequency is reduced due to the large capacitor and high transistor count
Solution Approach 1:
The patent removes the large bootstrap capacitor and several transistors from the traditional bootstrapping circuit. By extracting these components, the circuit achieves high-speed operation while maintaining constant on-resistance through an alternative mechanism using a controlled voltage source that provides the necessary gate-source voltage without requiring large energy storage elements.
Solution Approach 2:
Instead of using a large capacitor to store energy and maintain voltage (traditional approach), the patent inverts the approach by using an active voltage control mechanism that dynamically adjusts the gate-source voltage. This inversion allows the circuit to achieve the same on-resistance stabilization effect without the speed-limiting large capacitor.
2Manufacturing precision
If a traditional bootstrapping circuit with many transistors is used, then constant gate-source voltage is achieved, but parasitic capacitance increases and effective bandwidth is reduced
Solution Approach 1:
The patent extracts and removes multiple transistors from the traditional bootstrapping circuit configuration. By reducing the transistor count from typically 7-9 transistors to just 3 transistors, the circuit significantly reduces parasitic capacitance while maintaining the essential function of providing constant gate-source voltage through a simplified control mechanism.
Solution Approach 2:
The patent applies local quality by implementing voltage control only where necessary (at the gate-source of the sampling transistor) rather than using a complex global bootstrapping mechanism. This localized control approach achieves the required voltage constancy with minimal components, reducing overall circuit complexity and parasitic effects.
3Stability of the object's composition
If a large capacitor is used in the bootstrapping circuit, then gate-source voltage stability is improved, but the tracking time constant is reduced and speed is limited
Solution Approach 1:
The patent removes the large capacitor that limits the tracking speed. By extracting this energy storage element, the circuit achieves fast tracking response while maintaining voltage stability through an active control mechanism that can rapidly adjust the gate-source voltage without being constrained by capacitor charging/discharging time constants.
Solution Approach 2:
The patent transitions from a static voltage storage approach (large capacitor) to a dynamic voltage control approach. The controlled voltage source can rapidly adapt and adjust the gate-source voltage in real-time, providing both stability and fast response without the inherent time constant limitations of large capacitors.
Data Source
AI summary
A sampling switch circuit, comprising: an input node, connected to receive an input voltage signal to be sampled; a sampling transistor comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node; a potential divider circuit connected to the input node and a track-control node to provide a track-control voltage signal dependent on the input voltage signal at the track-control node; a hold-control node connected to receive a hold-control voltage signal; an output node connected to the drain terminal of the sampling transistor; and switching circuitry configured to connect the gate terminal of the sampling transistor to the track-control node or to the hold-control node in dependence upon a clock signal.