Sampling Switch Circuit With Constant Gate-Source Voltage
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Solution Overview
Problem
Existing sampling switch circuits face limitations in dynamic range due to input-dependent on-resistance variations, which can lead to harmonic distortion, especially when used as front-ends for analogue-to-digital converters (ADCs) in high-speed applications.
Innovation Solution
A sampling switch circuit design that employs a potential divider circuit and buffer circuits to maintain a constant gate-source voltage for the sampling transistor, independent of the input signal, thereby reducing on-resistance variations and enhancing tracking time constants, while also improving input impedance matching and reducing the need for bulky capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional bootstrapping circuit is used to maintain constant gate-source voltage, then on-resistance variations are reduced, but the circuit requires bulky capacitors and has limited operating frequency
Solution Approach 1:
The patent changes the control parameter from voltage-based bootstrapping to current-based control. By using a current source connected to the gate of the sampling transistor, the on-resistance is controlled through current magnitude rather than voltage, eliminating the need for large bootstrapping capacitors while maintaining constant on-resistance during the sampling phase.
Solution Approach 2:
The patent replaces the mechanical/electrical bootstrapping mechanism (using capacitors and switches to transfer charge) with a direct current control mechanism. The current source directly sets the gate voltage to maintain constant on-resistance, substituting the complex bootstrapping circuitry with a simpler current-controlled approach.
2Device complexity
If the sampling transistor on-resistance varies with input voltage, then the circuit is simpler, but harmonic distortion increases and dynamic range is limited
Solution Approach 1:
The patent implements feedback by monitoring the input voltage and using it to control the current source that drives the sampling transistor gate. This feedback mechanism ensures that the gate-source voltage adjusts to maintain constant on-resistance regardless of input voltage variations, thereby reducing harmonic distortion while keeping the circuit relatively simple.
Solution Approach 2:
The patent changes the operating parameter of the sampling transistor from voltage-controlled to current-controlled. By using a current source that responds to input voltage feedback, the on-resistance is maintained constant, reducing harmonic distortion without significantly increasing circuit complexity.
3Measurement precision
If a voltage mode sampler with bootstrapping is used, then tracking accuracy is improved, but the maximum operation frequency is reduced
Solution Approach 1:
The patent replaces the voltage-based bootstrapping mechanism with a current-controlled mechanism. This substitution removes the limitations imposed by large capacitors in the bootstrapping circuit, allowing for faster charging and discharging times, thereby increasing the maximum operation frequency while maintaining tracking accuracy through precise current control.
Solution Approach 2:
The patent changes the control mode from voltage-based to current-based, which fundamentally alters the dynamic response of the sampling circuit. The current source can respond more quickly to changes in the input signal, improving the tracking speed and maximum operation frequency while maintaining accuracy through feedback control.
Data Source
AI summary
A sampling switch circuit, comprising an input node, connected to receive an input voltage signal, a sampling transistor comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node, a hold-control node connected to receive a hold-control voltage signal, an output node connected to the drain terminal of the sampling transistor, a buffer circuit having a buffer input connected to the input node and a buffer output connected to a track-control node, the buffer circuit configured to provide a track-control voltage signal at the track-control node dependent on the input voltage signal and switching circuitry configured to connect the gate terminal of the sampling transistor to the track-control node or to the hold-control node in dependence upon a clock signal.