Sampling Time-to-Digital Converter Using Voltage Ramp Quantization
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Solution Overview
Problem
Conventional Time-to-Digital Converters (TDCs) are limited by gate delay resolution, which restricts their performance in applications like Phase Locked Loops (PLLs), especially in digital frequency synthesis, where higher resolution is necessary for accurate time interval measurements.
Innovation Solution
A method and circuit that utilize a time-varying analog voltage generator and an Analog-to-Digital Converter (ADC) to generate a digital signal representing time differences, with the resolution determined by the slew rate of the voltage ramp or cyclic waveform, allowing for improved time resolution through the use of a counter and encoder to quantify voltage levels and transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If gate delay-based TDC is used, then device complexity is reduced, but measurement precision deteriorates due to limited resolution
Solution Approach 1:
The patent replaces the mechanical gate delay-based timing mechanism with an electrical voltage ramp system. Instead of measuring time through sequential gate delays, the system converts time differences into voltage differences using a voltage ramp generator, which is then digitized by an ADC. This substitution enables higher resolution (down to 0.1 ps) without proportionally increasing circuit complexity.
Solution Approach 2:
The patent changes the measurement parameter from direct time measurement through gate delays to voltage measurement through a ramp signal. By generating a voltage ramp at a known slew rate and measuring the voltage difference corresponding to time intervals, the system achieves higher effective resolution. The ADC quantizes the voltage difference, and the time value is recovered by dividing by the slew rate, transforming the measurement domain from temporal to electrical.
2Loss of time
If more stages are added to delay line, then time range increases, but manufacturing precision deteriorates due to minimum gate delay limitations
Solution Approach 1:
The patent changes the fundamental measurement parameter from gate delay steps to voltage levels. The voltage ramp generator produces a continuous voltage signal that sweeps through a range, and the ADC quantizes this continuous signal into many discrete levels. This parameter change allows the system to achieve fine quantization resolution (0.1 ps equivalent) without being constrained by the minimum gate delay of the fabrication process, enabling both large time range and high precision simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves significantly lower time resolution, up to 100 times better than conventional TDCs, with resolutions as low as 0.1 ps, enhancing the performance of TDCs in applications like PLLs by overcoming the limitations of gate delay-based systems.
Implementation Method 1
The resolution of the digital representation of (t2−t1) may be determine by the slew rate
Data Source
AI summary
Disclosed is a time-to-digital (TDC) converter comprising an analog voltage source. An analog-to-digital converter quantizes two voltage samples in response to receiving a first input signal at a first time t1 and a second input signal at a second time t2. The first and second digital signals are combined to produce a digital signal that represents the difference (t2−t1).