Sampling Transistor Segmentation for Narrow Pitch Stability

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Solution Overview

Problem

In active matrix type liquid crystal display devices, the stability of the sample and hold circuit is compromised due to stress-induced cracks in the insulating film, particularly when transistors are disposed at a narrow pitch, leading to operational issues and display unevenness.

Innovation Solution

The solution involves configuring the sampling transistors with multiple transistors connected in parallel and a monitor transistor with a single transistor, along with a light shielding layer arrangement that disperses stress and prevents cracks, ensuring stable operation and reliable signal transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If transistors are disposed at a narrow pitch to increase pixel density, then high-definition display is achieved, but stress-induced cracks occur in the insulating film leading to circuit instability

Engineering Contradiction:
Improvepixel pitchVSAvoidcircuit stability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The sampling transistor is divided into multiple sub-transistors (first, second, third, and fourth sampling transistors) connected in parallel. This segmentation reduces the channel width of each individual transistor, allowing them to be disposed at narrower pitches without causing stress concentration that would lead to insulating film cracks, thereby maintaining circuit reliability while achieving high-definition display

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the circuit are designed with different transistor configurations. The sampling transistor region uses multiple divided transistors to prevent cracks, while the monitoring transistor uses a single transistor design. This local differentiation optimizes each region for its specific function while maintaining overall circuit stability at high pixel densities

Inventive Principle:
Principle #3Local quality

2Reliability

If multiple transistors are used in parallel for sampling, then circuit stability is improved, but device complexity increases

Engineering Contradiction:
Improvesample and hold circuit stabilityVSAvoidtransistor configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple sampling transistors are connected in parallel to form a single functional sampling unit. This merging approach distributes the sampling function across multiple transistors, improving reliability through redundancy and reduced stress on individual components, while the parallel configuration maintains the same external interface and control logic, thus managing complexity

Inventive Principle:
Principle #5Merging (Combining)

3Manufacturing precision

If gate electrodes are meandered to fit narrow pitch, then transistor density increases, but channel length variation occurs affecting operation stability

Engineering Contradiction:
Improvetransistor pitchVSAvoidoperation stability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

Instead of meandering a single gate electrode, the sampling transistor is segmented into multiple sub-transistors with straight, simple gate electrodes. This segmentation allows each sub-transistor to have a uniform and controlled channel length, eliminating the channel length variation that would result from meandering while still achieving narrow pitch through the parallel arrangement of multiple units

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10495935B2Electro-optical device and electronic apparatus with sampling and monitoring transistors
Publication Date: 2019.12.03 SEIKO EPSON CORP
  • US10495935B2 patent drawing
  • US10495935B2 patent drawing
  • US10495935B2 patent drawing

AI summary

An electro-optical device (e.g., a liquid crystal device) includes a data line connected to a switching element provided for each pixel, a sampling transistor that has a gate supplied with a selection signal, a source supplied with an image signal, and a drain connected to the data line, and a monitoring transistor. A gate of the monitoring transistor is supplied with an input signal. A delay signal indicating a delay amount of the selection signal is sent out from a drain of the monitoring transistor. The sampling transistor includes a plurality of transistors connected in parallel to each other along the data line. The monitoring transistor includes one transistor along the data line.