Sand-blasted Through Glass Vias for Thin Substrate Planarity
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Solution Overview
Problem
The existing methods for forming through glass vias (TGVs) in semiconductor device packages, particularly in thin glass substrates, often damage the substrate and compromise planarity, affecting subsequent processes such as capacitor formation due to the use of drilling techniques.
Innovation Solution
The implementation of a semiconductor device package structure that includes a substrate with a patterned conductive layer and insulation layers, where the TGVs are formed using a sand-blasting technique instead of drilling, reducing substrate damage and improving planarity by eliminating the need for a support film like Ajinomoto Build-up Film (ABF).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If drilling technique is used to form TGV in thin glass substrate, then TGV can be formed for electrical interconnection, but the glass substrate is damaged and planarity is compromised
Solution Approach 1:
The patent replaces the mechanical drilling system with a chemical etching system. Instead of using physical drill bits that mechanically remove material and cause substrate damage, the invention uses chemical solutions to selectively etch the glass substrate through predefined via locations, thereby forming TGVs without mechanical contact or stress that would compromise substrate planarity
Solution Approach 2:
The patent introduces a support/protection film as an intermediary layer between the drilling/etching process and the glass substrate. This film serves multiple functions: it protects the substrate from damage during processing, maintains substrate planarity, and provides a stable surface for subsequent capacitor formation processes
2Ease of manufacture
If support/protection film is applied to handle thin glass substrate, then substrate can be handled, but planarity of the film is not good enough and adversely affects subsequent process
Solution Approach 1:
The patent modifies the physical and chemical parameters of the support/protection film to improve its planarity. This includes optimizing film thickness, material composition, and deposition conditions to achieve a film that maintains substrate integrity while providing sufficient planarity for subsequent capacitor formation processes
3Reliability
If drilling operation is performed twice on substrate, then TGV can be formed in thin glass substrate, but substrate damage is increased
Solution Approach 1:
The patent replaces the mechanical drilling system with a chemical etching system that forms TGVs in a single step without the need for repeated operations. The chemical etching process selectively removes glass material through predefined via locations while maintaining substrate integrity, eliminating the cumulative damage associated with multiple drilling operations
Solution Approach 2:
The patent applies the support/protection film before the TGV formation process as a preliminary protective measure. This pre-applied film prevents substrate damage during the chemical etching process, allowing for successful TGV formation without compromising substrate strength or requiring repeated operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of semiconductor device packages with reduced package sizes and improved manufacturing efficiency by avoiding substrate damage and enhancing planarity, facilitating better integration of passive components and electrical interconnections.
Implementation Method 1
the TGVs are formed using a sand-blasting technique instead of drilling
Data Source
AI summary
A semiconductor device package includes: (1) a substrate having a first surface and a second surface opposite to the first surface; (2) a first patterned conductive layer on the first surface of the substrate and having a first surface and a second surface, wherein the second surface of the first patterned conductive layer is adjacent to the substrate and opposite to the first surface of the first patterned conductive layer; (3) a first insulation layer on the first surface of the substrate and having a first surface and a second surface, wherein the second surface of the first insulation layer is adjacent to the substrate and opposite to the first surface of the first insulation layer; and (4) a second patterned conductive layer extending from the first surface of the first insulation layer to the second surface of the substrate, the second patterned conductive layer electrically connected to the first patterned conductive layer.