Sandwich Capacitor Holes Boost Density
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Solution Overview
Problem
As semiconductor device features shrink, capacitor structures face challenges with reduced capacitance per unit area due to thinner gate oxide layers leading to increased gate leakage, and thicker oxide layers are used to mitigate this, resulting in lower capacitance and additional processing steps.
Innovation Solution
A sandwich capacitor structure is developed with a bottom silicon-containing conductor plate featuring holes or cavities, increasing capacitive area by forming a line or waffle-like structure, and etching techniques are used to taper the hole sides and adjust depth, allowing for higher capacitance per footprint area without additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If gate oxide layers are reduced in thickness to increase capacitance per unit area, then capacitance density improves, but gate leakage increases
Solution Approach 1:
The patent introduces holes or cavities through the bottom conductive layer, transforming the capacitor structure from a planar two-dimensional configuration to a three-dimensional structure. This dimensional change increases the effective capacitive surface area without increasing the footprint area, thereby improving capacitance per unit area while maintaining acceptable leakage characteristics through controlled oxide thickness in the hole regions
Solution Approach 2:
The patent creates a porous structure by forming an array of holes or cavities in the bottom conductive layer. This porous configuration increases the surface area available for capacitance formation while allowing control over the oxide layer thickness in different regions, enabling high capacitance density without excessive leakage
2Object-generated harmful factors
If thicker oxide layers are used to reduce gate leakage, then leakage decreases, but capacitance per unit area reduces
Solution Approach 1:
The patent applies different oxide layer thicknesses in different locations: thicker oxide layers in regions with holes or cavities to reduce leakage, and thinner oxide layers in planar regions to maintain high capacitance. This local differentiation of oxide thickness allows simultaneous optimization of both leakage reduction and capacitance density
Solution Approach 2:
By introducing vertical holes or cavities, the patent creates additional capacitive interfaces that increase the effective area for capacitance formation. This dimensional transformation allows the use of thicker oxide layers in hole regions for leakage control while maintaining overall high capacitance through the increased surface area
3Quantity of substance
If holes or cavities are added to increase capacitive area, then capacitance per footprint area increases, but processing complexity increases
Solution Approach 1:
The patent combines the hole formation process with existing etching and deposition steps in the semiconductor manufacturing flow. The holes are formed using standard etching techniques through patterned masks, and subsequent dielectric and conductive layers are deposited using conventional CVD or PECVD processes, merging the enhanced capacitor structure creation with existing process modules
Solution Approach 2:
The patent uses standard semiconductor processing equipment and materials for creating the enhanced capacitor structure. The same etching, deposition, and patterning tools used for transistor fabrication are utilized to create the holes and fill them with conductive material, making the process universally applicable without requiring specialized equipment
Data Source
AI summary
A process and device structure is provided for increasing capacitance density of a capacitor structure. A sandwich capacitor is provided in which a bottom silicon-containing conductor plate is formed with holes or cavities, upon which an oxide layer and a top silicon-containing layer conductor is formed. The holes or cavities provide additional capacitive area, thereby increasing capacitance per footprint area of the capacitor structure. The holes can form, for example, a line structure or a waffle-like structure in the bottom conductor plate. Etching techniques used to form the holes in the bottom conductor plate can also result in side wall tapering of the holes, thereby increasing the surface area of the silicon-containing layer defined by the holes. In addition, depth of holes can be adjusted through timed etching to further adjust capacitive area.