Modified SAQP Process Using Cut Pattern Masks for Reduced IC Cell Area
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Solution Overview
Problem
Conventional light-based lithography and self-aligned quadruple patterning (SAQP) processes face limitations in achieving further area reduction of integrated circuits (ICs) due to metal pitch constraints, which hinder miniaturization demands.
Innovation Solution
A modified SAQP process using a cut pattern mask is employed to dispose narrower voltage rails and reduce the number of routing lines by removing specific spacers, allowing for a smaller metal pitch and area reduction in IC cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional light-based lithography is used, then the process is simple and well-established, but the metal pitch is limited to 80 nm or larger due to wavelength constraints
Solution Approach 1:
The lithography process is segmented into multiple discrete steps (mandrel formation, first spacer deposition, second spacer deposition, cut pattern mask application) rather than attempting to achieve the final pattern in a single exposure. This segmentation allows each step to be optimized independently, achieving 28 nm metal pitch through cumulative pattern refinement.
Solution Approach 2:
Mandrels and spacers are formed in advance as sacrificial structures that define the final metal pattern locations. These preliminary structures are deposited and patterned before the actual metal layers are formed, allowing the final metal pitch to be determined by the spacer dimensions rather than direct lithographic resolution.
2Manufacturing precision
If conventional SAQP is used to achieve smaller metal pitch, then the metal pitch is reduced to approximately 28 nm, but the voltage rails and routing lines require larger area due to sizing limitations
Solution Approach 1:
The cut pattern mask applies different removal patterns to different regions of the second spacers. Specifically, spacers adjacent to voltage rail locations are removed while spacers adjacent to routing track locations are retained. This local differentiation allows voltage rails to be formed with narrower widths (matching the reduced metal pitch) while routing tracks maintain adequate spacing, optimizing the overall cell area.
Solution Approach 2:
Instead of forming voltage rails and routing lines by directly patterning metal layers with large minimum widths, the approach inverts the process by using selective spacer removal to define narrow voltage rail regions, then filling only those defined regions with metal. This inversion allows voltage rails to be narrower than the conventional metal pitch would permit.
3Manufacturing precision
If voltage rails are formed using conventional SAQP, then the metal pitch is reduced, but the voltage rails must be wider to maintain adequate current density, increasing area
Solution Approach 1:
The cut pattern mask creates local variations in the spacer structure by selectively removing spacers at voltage rail locations while retaining spacers at routing track locations. This local quality differentiation enables voltage rails to be formed with widths approximately equal to the metal pitch (28 nm) rather than requiring wider rails, thereby reducing the quantity of metal substance while maintaining current density requirements.
Data Source
AI summary
Aspects describing modified self-aligned quadruple patterning (SAQP) processes using cut pattern masks to fabricate integrated circuit (IC) cells with reduced area are disclosed. In one aspect, a modified SAQP process includes disposing multiple mandrels. First spacers are disposed on either side of each mandrel, and second spacers are disposed on either side of each first spacer. A cut pattern mask is disposed over the second spacers and includes openings that expose second spacers corresponding to locations in which voltage rails are to be disposed. The voltage rails are formed by removing the second spacers exposed by the openings in the cut pattern mask, and disposing the voltage rails in the corresponding locations left vacant by removing the second spacers. Routing lines are disposed over routing tracks formed between each set of the remaining second spacers to allow for interconnecting of active devices formed in the IC cell.