SAR ADC with Active Integrator for Low-Power High-Resolution Sensing
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) in sensor systems consume significant energy, limiting their operation in applications with limited power sources, and struggle with high parasitic capacitances and resolution, especially in capacitive sensor applications.
Innovation Solution
A successive-approximation register (SAR) ADC with an active integrator stage and a ring oscillator-based comparator, which operates in different phases to minimize energy consumption and tolerate parasitic capacitances, achieving high resolution and energy efficiency through noise-shaping and differential operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional ADC circuitry is used in sensor systems, then analog values can be converted to digital values, but energy consumption increases significantly
Solution Approach 1:
The ADC operation is divided into multiple phases (sampling phase and conversion phase) with distinct functions. The sampling phase captures the analog input signal, while the conversion phase performs the actual digital conversion through successive approximation. This segmentation allows the circuit to minimize energy consumption by activating only necessary components during each phase.
Solution Approach 2:
The SAR ADC employs periodic switching of capacitors during the conversion process, where capacitors are alternately connected to reference voltages and ground to generate successive approximation bits. This periodic action enables efficient bit-by-bit conversion while maintaining low power consumption through controlled switching sequences.
2Reliability
If conventional ADC designs are used, then conversion function is provided, but robustness against parasitic capacitances deteriorates
Solution Approach 1:
The patent deliberately incorporates dummy parasitic capacitances into the capacitor array and designs the SAR ADC to treat these harmful parasitic effects as useful components. By pre-compensating for parasitic capacitances during calibration and designing the switching network to account for parasitic effects, the circuit converts what would normally be harmful interference into a predictable, manageable parameter that can be compensated for in the conversion algorithm.
3Measurement precision
If conventional ADC circuitry is used, then digital conversion is achieved, but resolution decreases in capacitive sensor applications
Solution Approach 1:
The patent introduces an intermediary calibration process that measures and compensates for parasitic capacitances before the actual conversion. A calibration phase is inserted between sampling and conversion, where dummy capacitors are used to characterize parasitic effects. This intermediary step creates a correction map that is applied during conversion, effectively eliminating the degrading influence of parasitic capacitances on resolution.
Data Source
AI summary
Circuitry and techniques are described herein for performing accurate and low power conversion of an analog value into a digital value. According to some aspects, this disclosure describes a successive approximation register (SAR) analog to digital converter (ADC). According to some aspects the SAR ADC comprises an active integrator between a sample and hold stage and a comparator stage. The active integrator operates differently dependent on whether the SAR ADC is operated in a sample phase or a conversion phase. According to other aspects, the SAR ADC utilizes a ring oscillator-based comparator to compare a sampled analog input value to a plurality of reference values to determine a digital value representing the analog value.