SAR-ADC Capacitor Array Filtering for Receiver Aliasing Suppression
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Solution Overview
Problem
Direct conversion sampling receivers suffer from frequency spikes due to aliasing components, particularly around the 3*Flo range, leading to decreased attenuation and noise folding onto the desired channel, and lack adaptive filtering capabilities to address varying signal conditions.
Innovation Solution
The implementation of a charge redistribution SAR-ADC architecture with redeployable capacitor arrays and independent gain stages allows for adaptive filtering by independently setting frequency, phase, and mark space ratios of sampling clock signals, enabling enhanced harmonic attenuation and filtering across the frequency spectrum.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If direct conversion sampling receiver architecture is used, then the receiver can be implemented on ultra-high speed digital process without significant analogue circuits, but frequency spikes occur due to aliasing components around 3*Flo range
Solution Approach 1:
The patent converts the harmful aliasing components into useful filtering information by using the SAR-ADC's capacitor arrays to deliberately create notches at specific frequency locations (including 3*Flo) where aliasing occurs. The capacitor switching mechanism generates counter-phase signals that cancel the aliasing frequency spikes, transforming the harmful effect into a beneficial filtering action.
Solution Approach 2:
The patent changes the electrical parameters (capacitor switching states, phase relationships, and timing) of the SAR-ADC circuit to dynamically create filtering notches at specific frequency locations. By adjusting the capacitor array configuration and switching timing, the system adapts to different aliasing conditions and maximizes attenuation at problematic frequencies.
2Device complexity
If conventional direct conversion receiver architecture is used, then the structure is simplified, but the characteristic response cannot be easily modified to adaptively modify attenuation at given frequency
Solution Approach 1:
The patent introduces dynamic control into the SAR-ADC capacitor arrays, allowing the filtering characteristics to be adjusted in real-time based on received signal conditions. The capacitor switching mechanism can be dynamically reconfigured to move notches to different frequency locations, enabling adaptive response to varying aliasing patterns while maintaining the basic simplicity of the direct conversion architecture.
Solution Approach 2:
The patent makes the SAR-ADC capacitor arrays serve dual functions: their primary function for digital-to-analog conversion during normal operation, and a secondary function as programmable filters when configured in the filtering mode. This multi-functionality provides adaptive filtering capability without adding separate dedicated filtering hardware, maintaining structural simplicity.
3Productivity
If sampling is performed at Flo, then digital processing is enabled, but aliasing components fold onto desired channel increasing noise and discrete signals
Solution Approach 1:
The patent introduces the SAR-ADC capacitor arrays as an intermediary filtering stage between the sampling process and the desired signal output. These capacitor arrays act as a mediator that selectively attenuates aliasing frequency components before they can fold onto and contaminate the desired channel, while preserving the digital processing capability enabled by the sampling operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly improves attenuation at harmonic frequencies, reduces aliasing components, and allows for adaptive filtering responses, effectively mitigating noise and signal interference across the frequency spectrum.
Implementation Method 1
a current redistribution digital-to-analog converter (DAC) where filtering is implemented in the radio frequency (RF) domain by at least reusing a capacitor arrays which form all or part of the DAC within the SARADC
Data Source
AI summary
An apparatus and method of successive approximation analog-to-digital conversion for receivers comprising that during a sample mode, connecting an array of capacitors to a plurality of sampling switches coupled to a plurality of amplified input signals, and during a conversion mode, connecting in common the array of capacitors to a comparator and isolating the array of capacitors from the plurality of sampling switches. Additionally, filtering is done by the summation of samples at phase offsets.