SAR ADC Offset Calibration Using Alternating Sampling Cycles
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Solution Overview
Problem
Successive approximation register analog-to-digital converters (SARADCs) face challenges in accurately converting analog signals due to voltage offsets caused by physical characteristics, operating voltages, and ambient temperatures, which existing calibration methods either consume high power or require frequent recalibration.
Innovation Solution
A method and circuit that alternately samples analog input signals and calibration signals to calculate and apply an N-bit offset value, using a sample/hold circuit, comparator, and calibration circuit to determine and update offset values for each bit, allowing for continuous calibration during operation with low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional calibration methods are used to correct voltage offsets, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic calibration by alternating between calibration mode and normal conversion mode. The sample/hold circuit periodically samples calibration voltages to update offset values for each bit, rather than continuously calibrating. This periodic action maintains measurement precision while significantly reducing average power consumption compared to continuous calibration methods.
2Measurement precision
If frequent recalibration is performed to maintain accuracy under varying operating conditions, then measurement precision is improved, but productivity deteriorates
Solution Approach 1:
The patent segments the N-bit offset value into individual bit components, where each bit has its own calibration value stored in a separate calibration register. This allows selective updating of only the necessary bits during calibration, rather than recalibrating the entire N-bit value, thereby maintaining accuracy while minimizing impact on conversion rate.
Solution Approach 2:
The calibration process is performed periodically in alternating cycles with normal ADC conversion operations. During calibration cycles, the sample/hold circuit samples calibration voltages; during conversion cycles, normal operations proceed uninterrupted. This periodic alternation ensures accuracy under varying conditions while maintaining high overall productivity.
3Measurement precision
If complete N-bit offset calibration is performed for each input sample, then measurement precision is improved, but time consumption increases
Solution Approach 1:
The patent applies partial calibration by determining only the necessary number of bits of the offset value for each input sample rather than always performing complete N-bit calibration. The calibration circuit calculates offset bits progressively, and once sufficient precision is achieved, normal conversion resumes. This partial action approach maintains measurement precision while minimizing time loss.
Data Source
AI summary
An analog input signal is sampled, and the sampled analog input signal is converted to a digital value. A calibration value is also sampled, and a single bit of an N bit offset value is calculated from the sampled calibration value. The sampling operations are alternatively performed so that one bit of the offset value is generated for each generated digital value. For example, the process is repeated N times to calculate all N bits of the offset value while generating N digital values.