SAR ADC Arbitration Circuit for 2-Bit Conversion With Fewer Comparators
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Solution Overview
Problem
Conventional 2-bit-per-cycle SAR ADCs require three capacitor arrays and three comparators, leading to complexity and calibration challenges due to mismatch/offset issues, making calibration difficult and necessitating a design with fewer components to mitigate these problems.
Innovation Solution
A SAR ADC design utilizing only two capacitor arrays and two comparators, along with an arbiter and control circuit, where the arbiter generates an arbitration result based on comparison results from both comparators to determine output signals, thereby simplifying calibration and reducing component mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three capacitor arrays and three comparators are used in conventional 2-bit-per-cycle SAR ADC, then the ADC can determine two bits per cycle, but the mismatch/offset between components increases and calibration complexity increases
Solution Approach 1:
The patent merges the functionality of three capacitor arrays into two capacitor arrays, and three comparators into two comparators, while maintaining the 2-bit-per-cycle conversion capability. This is achieved by sharing capacitor arrays between different comparison operations and using an arbiter to coordinate the comparison results from the reduced number of comparators.
Solution Approach 2:
Each capacitor array is designed to serve multiple functions - the first capacitor array is used for both first comparison and second comparison operations, and the second capacitor array similarly serves dual purposes. This multi-functionality reduces the total number of capacitor arrays needed while maintaining the required comparison capabilities for 2-bit resolution.
2Measurement precision
If three capacitor arrays and three comparators are used, then 2-bit resolution is achieved, but calibration difficulty increases due to more components
Solution Approach 1:
By combining the comparison operations into fewer comparators (two instead of three), the patent reduces the number of components that require individual calibration, thereby simplifying the overall calibration process while maintaining 2-bit resolution through coordinated operation of the reduced component set.
Solution Approach 2:
The arbiter acts as an intermediary that coordinates the comparison results from the two comparators to achieve the required 2-bit resolution. This mediator component manages the interaction between the reduced number of comparators and capacitor arrays, ensuring accurate conversion without requiring calibration of each individual component in a large array.
3Reliability
If more capacitor arrays and comparators are used, then conversion accuracy is maintained, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple capacitor arrays and comparators into a reduced set of two capacitor arrays and two comparators, directly reducing the bill of materials and manufacturing cost. The conversion accuracy is maintained through the coordinated operation of these reduced components under the control of the arbiter and control circuit.
Solution Approach 2:
The patent changes the operational parameters and control logic to accommodate the reduced number of hardware components. By modifying the control sequence and arbitration logic, the system achieves the same conversion accuracy with fewer physical components, thereby reducing manufacturing cost.
Data Source
AI summary
A SAR ADC includes a first capacitor array, a first comparator, a second capacitor array, a second comparator, an arbiter and a control circuit. The first capacitor array is arranged for receiving an input signal to generate a first signal. The first comparator is arranged for comparing the first signal with a first reference signal to generate a first comparison result. The second capacitor array is arranged for receiving the input signal to generate a second signal. The second comparator is arranged for comparing the second signal with a second reference signal to generate a second comparison result. The arbiter is arranged for generating an arbitration result according to the first comparison result and the second comparison result. The control circuit is arranged for generating an output signal according to the first comparison result, the second comparison result and the arbitration result.