SAR ADC BER Forecast Circuit Using Extra Conversion Operations
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Solution Overview
Problem
The lengthy testing time required to verify the bit error rate of high-performance analog-to-digital converters, such as those in gigabit Ethernet circuits, is not cost-effective, as it can take several days to ensure the converters meet stringent performance requirements like a bit error rate lower than 1/1015.
Innovation Solution
A bit error rate (BER) forecast circuit for successive approximation register analog-to-digital conversion, which includes an N bits SAR ADC and an estimation circuit that performs additional operations within a conversion cycle, generating a test value related to the BER based on time differences between regular and additional operations, allowing for faster evaluation of BER and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional testing methods are used to verify bit error rate, then measurement precision is improved, but loss of time increases significantly
Solution Approach 1:
The patent performs preliminary operations within the conversion cycle by executing additional operations (beyond the standard N bits conversion) during the same time period. The SAR ADC performs N bits regular operation plus X additional operations in one conversion cycle, allowing early detection of potential bit errors before full conversion time elapses. This preliminary action enables time-saving forecast without sacrificing measurement precision.
Solution Approach 2:
The patent creates a simplified test model that copies the essential conversion process but operates at accelerated speed. By performing multiple regular operations (Y rounds) that are shorter than full conversion time, the system generates test values that replicate the behavior of full-speed conversion but in compressed time frames, enabling fast BER forecasting.
2Loss of time
If conversion time is reduced to save testing time, then loss of time is improved, but measurement precision deteriorates
Solution Approach 1:
The patent employs periodic action by performing Y rounds of regular operations, where each round takes less than full conversion time. These repeated periodic operations generate multiple test values that collectively provide statistically significant BER forecasting data, maintaining measurement precision while reducing individual operation time.
Solution Approach 2:
The patent applies partial action by performing only the essential N bits conversion operations plus X additional operations within the conversion cycle, rather than completing full conversion for every measurement. This partial execution is sufficient to generate forecast data, and performing Y rounds of this partial action provides adequate statistical accuracy for BER estimation.
Data Source
AI summary
Disclosed is a bit error rate (BER) forecast circuit for successive approximation register analog-to-digital conversion. The BER forecast circuit includes an N bits successive approximation register analog-to-digital converter (N bits SAR ADC) and an estimation circuit. The N bits SAR ADC is configured to carry out a regular operation at least N times and an additional operation at least X time(s) in one cycle of conversion time, in which the N is an integer greater than 1 and the X is an integer not less than zero. The estimation circuit is configured to generate a test value according to total times the N bits SAR ADC carrying out the additional operation in Y cycles of the conversion time, in which the Y is a positive integer and the test value is related to the bit error rate of the N bits SAR ADC.