Fast Settling Bias Circuit Using SAR-ADC Loop
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Solution Overview
Problem
Conventional bias circuits face challenges in quickly returning to an operational power state due to heavy bypassing for noise filtering, leading to slow power-on processes and excessive power consumption, along with issues of ringing in the supply voltage caused by current surges.
Innovation Solution
A successive-approximation-register-analog-to-digital converter (SAR-ADC) based settling loop is used to rapidly settle a heavily loaded bias node by measuring references and performing charge sharing between capacitors, eliminating large current surges and improving power integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If heavy bypass capacitance is added to filter noise at the bias node, then noise immunity is improved, but the power-on time increases and the bias circuit settles slower
Solution Approach 1:
A buffer circuit is introduced as an intermediary between the bias node and the bypass capacitance. This buffer isolates the capacitive load from the bias node, allowing heavy bypass capacitance to be used for noise filtering without slowing down the power-on time or settling time of the bias circuit.
Solution Approach 2:
The circuit is segmented into two parts: the bias node that requires fast settling and the noise filtering function. The buffer circuit separates these functions, allowing the bias node to settle quickly while the bypass capacitance provides noise filtering without affecting the settling time.
2Use of energy by moving object
If the bias circuit is disabled to save power in low-power modes, then power consumption is reduced, but the circuit cannot quickly return to operational state when needed
Solution Approach 1:
The buffer circuit is pre-configured with the bypass capacitance already connected and charged. When the bias circuit needs to be reactivated from a low-power state, the buffer is already in place to immediately drive the bypass capacitance, eliminating the delay that would otherwise occur during power-up.
3Speed
If large current surge is used to quickly establish bias voltage during power-up, then power-on speed is improved, but ringing occurs in the supply voltage due to inductance and capacitance
Solution Approach 1:
The buffer circuit acts as an intermediary that controls the current flow to the bypass capacitance. It provides a controlled current surge that is sufficient to quickly establish the bias voltage during power-up, but is regulated to prevent excessive current that would cause ringing in the supply voltage due to inductance and capacitance interactions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SAR-ADC based loop enables fast and efficient power delivery, reducing power consumption and minimizing supply voltage ringing, allowing for quicker power-up and enabling bias circuits to be disabled for low-power modes without compromising noise immunity.
Implementation Method 1
measuring references and performing charge sharing between capacitors
Data Source
AI summary
Aspects of the present disclosure include systems, methods, devices, and circuits for fast settling of a bias node. Consistent with some embodiments, a bias circuit may include a successive-approximation-register-analog-to-digital converter (SAR-ADC) based settling loop configured to perform a fast settling process for a heavily loaded bias node. The SAR-ADC based loop performs a SAR-ADC process that includes measuring a reference signal to determine a number of cells in a capacitor array that are involved in a charge sharing process while simultaneously completing the settling process for the bias node.