SAR ADC Bit-Step Testing for Faster Coverage Verification

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Solution Overview

Problem

Traditional testing methods for analog-to-digital converters require a large number of bit tests across the entire range of input voltages, making the process time-consuming and resource-intensive.

Innovation Solution

The implementation of a bit step selector that identifies the most significant bit changing between digital values, allowing only those bits of significance equal to or less than the most significant bit to be tested for the next input voltage, significantly reducing the number of digital values tested.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional testing methods are used to test all bits across the entire input voltage range, then comprehensive testing coverage is achieved, but the testing process becomes time-consuming and resource-intensive

Engineering Contradiction:

Improvetesting coverageVSAvoidtesting time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the bit testing process by dividing bits into two groups: those that change value (requiring testing) and those that remain constant (exempt from testing). The bit step selector identifies and isolates only the relevant bits that need testing, separating them from the bits that can be skipped, thereby reducing the overall testing scope while maintaining coverage of critical functionality

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by testing only a subset of bits rather than all bits. Specifically, it tests only those bits whose values change between consecutive digital outputs, performing exactly the necessary testing without excessive action on bits that remain constant, thus optimizing the balance between testing thoroughness and efficiency

Inventive Principle:

Principle #16Partial or excessive action

2Reliability

If all bits are tested for every input voltage change, then complete verification is achieved, but computing resources are wasted on redundant tests

Engineering Contradiction:

Improveverification completenessVSAvoidcomputing resource consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements feedback by using the output of the previous voltage test (which bits changed) to inform the next test configuration. The bit step selector receives feedback about which bits changed in the previous step and uses this information to configure the next test, creating a closed-loop system that adapts testing based on actual converter behavior and avoids redundant resource consumption

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent changes the testing parameter from a static approach (testing all bits regardless of actual changes) to a dynamic approach where the set of tested bits changes based on the actual output behavior of the converter. The bit step selector dynamically adjusts which bits are tested by identifying those whose values change, thereby optimizing resource usage while maintaining verification completeness

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11463098B2Method and device for testing successive approximation register analog-to-digital converters

Publication Date: 2022.10.04 STMICROELECTRONICS INT NV

AI summary

An integrated circuit includes a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC includes a bit step selector. During testing of the ADC, the bit step selector selects a number of bits to be tested for a next analog test voltage based on digital values that are within an integer delta value of most recent digital value for a most recent analog test voltage.