SAR ADC Variable Bit Timing With Resistor Ladder Reference Shifting
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Solution Overview
Problem
Successive approximation register (SAR) analog to digital converters (ADCs) are typically slower than flash and pipelined ADCs, making them less suitable for designs with power and area constraints, due to their longer conversion times.
Innovation Solution
Implementing a variable rate conversion method where the evaluation time for bits in the digital representation is shorter for less significant bits (LSBs) than for more significant bits (MSBs), allowing for a faster clock cycle allocation and using a resistor ladder DAC with reference shifting to reduce area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If variable rate conversion is implemented with shorter evaluation time for LSBs, then conversion speed is improved, but conversion precision may be compromised
Solution Approach 1:
The patent implements dynamic evaluation time allocation where the evaluation time period varies for different bit positions. Specifically, the evaluation time for the least significant bit (LSB) is made shorter than that for the most significant bit (MSB), creating a dynamic conversion process that adapts time resources according to bit significance. This dynamic approach resolves the contradiction by providing sufficient evaluation time for critical MSBs while reducing time for less critical LSBs, thereby improving overall conversion speed without sacrificing essential precision.
Solution Approach 2:
The patent applies different evaluation time periods to different parts of the digital representation (different bit positions). The MSBs receive longer evaluation time periods to ensure high precision, while the LSBs receive shorter evaluation time periods. This local differentiation of quality (evaluation time) across different bit positions allows the system to optimize overall conversion speed while maintaining necessary precision for each bit position based on its significance.
2Measurement precision
If more clock cycles are allocated to bits with longer evaluation times, then conversion accuracy is improved, but overall conversion time increases
Solution Approach 1:
The patent employs a dynamic clock cycle allocation strategy where the number of clock cycles assigned to each bit evaluation varies based on the bit's significance and required evaluation time. The system uses a variable rate conversion approach that dynamically adjusts the conversion process to allocate more clock cycles to MSBs requiring longer evaluation, while using fewer clock cycles for LSBs with shorter evaluation requirements. This dynamic resource allocation improves conversion accuracy for critical bits while reducing overall conversion time.
Solution Approach 2:
The patent applies partial action by allocating clock cycles selectively rather than uniformly to all bit evaluations. The system provides excessive (more than minimum required) clock cycles to MSBs where high precision is critical, while using only partial (minimum sufficient) clock cycles for LSBs where less precision is acceptable. This selective partial/excessive action optimizes the trade-off between conversion accuracy and overall conversion time.
Data Source
AI summary
An analog to digital converter converts an input analog signal to a digital representation using successive approximation logic to generate a plurality of digital values approximating the analog signal. Evaluation logic evaluates each of the digital values by converting each of the digital values in a digital to analog converter (DAC) to a DAC analog signal and comparing the DAC analog signal to the input analog signal to determine a comparison result used by the successive approximation logic to generate a next one of the digital values. An evaluation time period for one or more bits of the digital representation is longer than for one or more other bits in the digital representation. The DAC includes a resistor ladder. Reference voltages of the DAC are increased for evaluation of the least significant bit (LSB) to obtain more accurate results without increasing a number of resistors.