SAR ADC With Embedded IIR Filter for Blocking Signal Rejection
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Solution Overview
Problem
Wireless local area network (WLAN) wake-up radios face challenges in reducing power consumption and circuit size due to the presence of blocking signals, which existing technologies address inadequately using discrete filters that increase cost and power consumption.
Innovation Solution
Implementation of a successive approximation register (SAR) analog-to-digital converter (ADC) with an embedded infinite impulse response (IIR) filter that attenuates blocking signals using digital sample feedback to a capacitive digital-to-analog converter (CDAC), eliminating the need for additional filters and reducing die area and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If discrete filters are used to attenuate blocking signals, then signal filtering performance is improved, but power consumption and circuit size increase
Solution Approach 1:
The patent combines the filtering function with the existing SAR ADC circuit by implementing an embedded IIR filter that utilizes the CDAC and its capacitors. The filter is integrated into the ADC architecture, sharing hardware resources rather than adding separate discrete filter components. This merging approach provides blocking signal attenuation while avoiding the additional power consumption and circuit size associated with external discrete filters.
2Object-affected harmful factors
If discrete filters are used to attenuate blocking signals, then signal filtering performance is improved, but circuit size and cost increase
Solution Approach 1:
The filtering function is merged with the SAR ADC circuitry by implementing the IIR filter using the existing CDAC capacitors and switches. The filter coefficients are programmed into the capacitor array, allowing the same hardware to serve both ADC conversion and signal filtering purposes. This eliminates the need for additional discrete filter components and reduces overall circuit size.
Solution Approach 2:
The CDAC and its capacitor array are designed to perform multiple functions: they serve as the core component for the SAR ADC conversion process and simultaneously function as the filter elements for the embedded IIR filter. This multi-functionality allows a single circuit block to provide both analog-to-digital conversion and blocking signal attenuation, reducing total circuit size and component count.
3Object-affected harmful factors
If discrete filters are used to attenuate blocking signals, then signal filtering performance is improved, but device complexity increases
Solution Approach 1:
The patent merges the filtering operation with the ADC conversion process by implementing the IIR filter within the SAR ADC timing and control structure. The filter computation is performed using the same control signals and timing phases that drive the ADC conversion, eliminating the need for separate filter control logic and reducing overall device complexity.
Data Source
AI summary
An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.