SAR ADC Buffer Control for Sampling Stability and Conversion Bandwidth
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Solution Overview
Problem
Successive Approximation Register Analog-to-Digital Converters (SAR ADCs) face design difficulties due to extreme capacitor loading during the sampling phase and insufficient bandwidth during the conversion phase, limiting their performance and resolution.
Innovation Solution
A special buffer design that adjusts the Miller compensation capacitor based on operational phases, increasing capacitance during the sampling phase for stability and reducing it during the conversion phase to ensure sufficient bandwidth for accurate signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the buffer is designed to drive extremely large capacitor loading during sampling phase, then the buffer can properly operate in sampling phase, but the bandwidth becomes insufficient during conversion phase
Solution Approach 1:
The patent applies dynamics by making the Miller compensation capacitor adjustable rather than fixed. The buffer dynamically changes the capacitance value of the Miller compensation capacitor based on the operating phase: using a first capacitance value during sampling phase to handle large capacitor loading, and a second capacitance value during conversion phase to ensure sufficient bandwidth. This dynamic adjustment resolves the contradiction between reliability in sampling phase and speed in conversion phase.
2Stability of the object's composition
If the Miller compensation capacitor uses large capacitance value, then the buffer stability improves for driving large capacitor loading, but the bandwidth decreases
Solution Approach 1:
The patent applies parameter changes by varying the capacitance value of the Miller compensation capacitor according to the operating phase. During sampling phase, a first capacitance value is used to provide stability when driving large capacitor loading. During conversion phase, a second capacitance value is used to increase bandwidth. This parameter adjustment resolves the contradiction between stability and bandwidth requirements in different operating conditions.
Data Source
AI summary
A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is disclosed. The SAR ADC includes a switched capacitor array, a buffer, a comparator and a control logic circuit. The switched capacitor array is arranged to sample an input signal according to a switch control signal to generate a sampling signal. The buffer is arranged to generate a common mode voltage. The comparator is arranged to receive the sampling signal and the common mode voltage in order to generate a comparison result. The control logic circuit is arranged to generate an output signal according to the comparison result, and generate the switch control signal to control the switched capacitor array. The control logic circuit further generates an operation control signal to adjust a Miller compensation capacitor inside the buffer. An associated control method is also disclosed.