SAR ADC Reference Buffer Tuning for Low-Power Bit Conversion
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Solution Overview
Problem
Conventional SAR_ADCs face high power consumption due to power-hungry analog blocks like the comparator, DAC, and reference buffer, while redundancy to alleviate settling and noise requirements increases complexity and cost.
Innovation Solution
A SAR_ADC with an adaptive power tuning circuit that dynamically adjusts the drive strength of the reference buffer and comparator based on the bit being resolved, using redundant capacitors for MSBs and variable-capacitance elements for LSBs to reduce power without increasing complexity or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SAR_ADC designs use power-hungry analog blocks (comparator, DAC, reference buffer) to meet minimum noise and settling requirements, then settling and noise performance is maintained, but power consumption increases
Solution Approach 1:
The reference buffer employs dynamic drive strength adjustment where the drive capability is varied based on the current conversion stage. During early conversion stages when larger voltage adjustments are needed, the reference buffer provides higher drive strength. In later stages when finer adjustments are required, the drive strength is reduced, thereby lowering power consumption while maintaining the necessary settling and noise performance throughout the conversion process.
Solution Approach 2:
The comparator uses variable gain amplification where the gain is adjusted according to the specific bit being resolved. For less significant bits where higher precision is needed, the comparator gain is increased to maintain noise performance. For more significant bits where larger voltage differences exist, the gain can be reduced, lowering power consumption while still meeting the required comparison accuracy.
2Reliability
If redundancy is introduced in the DAC to alleviate settling and noise requirements, then settling and noise performance improves, but device complexity and cost increase
Solution Approach 1:
Instead of adding redundant capacitors to the DAC, the invention changes the operational parameters of the existing DAC components. The reference buffer's drive strength is dynamically adjusted based on conversion stage, and the comparator's gain is varied according to the bit being resolved. These parameter changes allow the system to achieve improved settling and noise performance without modifying the fundamental DAC structure or adding redundant elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces power consumption by up to 30% while maintaining settling and noise performance, achieving faster settling times and improved accuracy without additional complexity or cost.
Implementation Method 1
a capacitive digital-to-analog converter (DAC)
Implementation Method 2
The comparator compares VDAC to VIN
Data Source
AI summary
A Successive Approximation Analog-to-Digital Converter (SAR_ADC) and method of operating the same are provided. Generally, the SAR_ADC includes a comparator having a first input to receive an input voltage (VIN), and a second input coupled to a n-bit capacitive digital-to-analog converter (DAC) to receive a voltage (VDAC), a Successive Approximation Register (SAR) coupled to a comparator output to provide n digital control signals to the DAC, and to store and output an n-bit binary-number approximating VIN, and a reference buffer to provide a voltage (VREF) to the DAC. The DAC sequentially drives each capacitance beginning with a most significant bit towards VREF, while the comparator compares the resulting VDAC to VIN, and the SAR sets or clears a current bit represented by the capacitance driven. The reference buffer includes adaptive power tuning to dynamically tune a drive-strength of the reference buffer based on the current bit.