SAR ADC Comparator Bulk Compensation for Parasitic Capacitance
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Solution Overview
Problem
Conventional amplifiers suffer from reduced linearity due to parasitic capacitances in transistors, which negatively impact connected circuits and cause performance degradation or errors.
Innovation Solution
A compensation circuit and method for successive-approximation register (SAR) analog-to-digital converters (ADCs) that includes a voltage generator to provide specific voltages to the transistors' bulk during sampling and comparison phases, mitigating parasitic capacitances and improving linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are used in conventional comparator circuits, then the circuit can perform comparison functions, but parasitic capacitances are generated that reduce linearity and cause performance degradation
Solution Approach 1:
The patent applies bulk voltage compensation to convert the harmful effect of parasitic capacitance into a beneficial outcome. By applying specific bulk voltages to the transistors during different phases (sampling and comparison), the parasitic capacitance effects are compensated for, improving linearity. This transforms the inherent parasitic effect into an opportunity for performance enhancement through active compensation.
Solution Approach 2:
The patent changes the bulk voltage parameter of the transistors dynamically during operation. Different bulk voltages are applied during the sampling phase versus the comparison phase to optimize performance. This parameter change approach allows the circuit to maintain low parasitic capacitance effects while preserving the necessary transistor functionality for comparison operations.
2Ease of operation
If parasitic capacitance is present in transistors, then the circuit operates, but linearity is reduced and connected circuits suffer performance degradation
Solution Approach 1:
The bulk voltage compensation technique converts the harmful parasitic capacitance effect into a benefit by actively compensating for its influence. The compensation circuit measures or estimates the parasitic capacitance effect and applies counteracting bulk voltages to eliminate the linearity degradation, thereby improving overall circuit precision while maintaining ease of operation.
Solution Approach 2:
The bulk voltage acts as an intermediary parameter that mediates between the transistor's inherent parasitic capacitance and the desired linearity performance. By controlling the bulk voltage, the circuit can adjust the effective parasitic capacitance impact, serving as a mediator that allows the circuit to operate easily while achieving high linearity precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The compensation circuit enhances the linearity of SAR ADCs by reducing the impact of parasitic capacitances, thereby improving total harmonic distortion, integral nonlinearity, and differential nonlinearity.
Implementation Method 1
The transistors M1 and M2 have parasitic capacitances, and capacitance values of the parasitic capacitances are a function of the input signal (VIP or VIN).
Data Source
AI summary
A compensation circuit is applied to a successive-approximation register (SAR) analog-to-digital converter (ADC) (SAR ADC) that includes a comparator, and the comparator includes a first transistor and a second transistor. The first transistor and the second transistor receive an input signal during a sampling phase, and the comparator determines at least one bit of a digital output code during a comparison phase. The compensation circuit includes a voltage generator coupled to the comparator for providing a first voltage to a first bulk of the first transistor and a second bulk of the second transistor during the sampling phase and providing a second voltage to the first bulk of the first transistor and the second bulk of the second transistor during the comparison phase.