SAR ADC Control Circuit With Comparator Bypass Data Path
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Solution Overview
Problem
The speed and performance of successive approximation register analog-to-digital converters (SAR ADCs) are hindered by significant signal delay in the memory and buffer components of the control circuit, particularly in the critical path between the input of the sub-control circuit and the switch of the switched-capacitor DAC.
Innovation Solution
A data path is introduced that temporarily bypasses the memory, allowing the voltage at the capacitor's first end to be controlled directly by the comparator's output, and later by the stored value, thereby reducing signal delay and enhancing circuit speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory and buffer components are used in the control circuit, then data storage and signal processing are improved, but signal delay increases significantly
Solution Approach 1:
The patent applies preliminary action by pre-charging the capacitor to a predetermined voltage level before the comparison operation begins. This preparation is done in advance during a setup phase, so that when the comparison and switching operations occur, the capacitor is already ready to switch states without waiting for charging time during the critical comparison path. This eliminates the charging delay from the critical path while maintaining the necessary capacitor functionality.
Solution Approach 2:
The patent segments the capacitor control into two independent phases: (1) a setup phase where the capacitor is pre-charged to a predetermined voltage, and (2) a comparison phase where the capacitor voltage is switched based on comparator output. This segmentation allows the time-consuming pre-charging operation to occur outside the critical comparison path, while the switching operation during comparison uses previously charged capacitors, thus reducing overall signal delay.
2Stability of the object's composition
If the capacitor voltage is controlled by the stored value in memory, then data stability is improved, but the switching speed is reduced
Solution Approach 1:
The patent pre-charges the capacitor to a predetermined voltage level before the comparison operation. This preliminary charging action ensures the capacitor is ready to switch immediately when the comparison result is available, without waiting for charging during the critical path. The pre-charged capacitor maintains stable voltage during the comparison phase, and can switch rapidly when needed.
Solution Approach 2:
The patent introduces a predetermined voltage level as an intermediary state for the capacitor. Instead of directly switching between full charge and discharge states based on memory values, the capacitor first reaches a predetermined intermediate voltage level, then switches from there based on the comparison result. This intermediary pre-charging step decouples the charging time from the switching time, allowing rapid switching while maintaining voltage stability during comparison.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the delay in the SAR ADC's critical path, leading to improved speed and performance by allowing the voltage at the capacitor to change earlier, thus enhancing the signal-to-noise-and-distortion ratio (SNDR).
Implementation Method 1
the comparator 120 compares a voltage corresponding to the digital code with the input signal to generate a comparison result
Implementation Method 2
the control signal G controls the terminal voltage of the capacitors in the switched-capacitor DAC 110, so that the charges on the capacitors redistribute, leading to a change in the voltage at the inverting input or non-inverting input of the comparator
Data Source
AI summary
This invention discloses a control circuit and a control method of a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The control circuit includes a memory, an inverter and a data path. The memory is configured to store an output value of the comparator. The inverter has an output coupled to a first end of a capacitor of the switched-capacitor DAC. A second end of the capacitor is coupled to an input of the comparator. The data path, coupled between an output of the comparator and an input of the inverter, temporarily causes a voltage at the first end of the capacitor to be controlled by the output value of the comparator. The data path does not contain any memory.