Successive Approximation A/D Converter Capacitance Circuit

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Solution Overview

Problem

Successive approximation type A/D converters face challenges in minimizing power consumption and ensuring accurate full-scale range operation due to parasitic capacitances and process variations, which affect their dynamic range and conversion accuracy.

Innovation Solution

The design incorporates a capacitance circuit with a combination of fixed and variable capacitances, including a parallel connection of fixed and variable capacitance units, and switches to adjust the capacitance value, ensuring the full-scale range corresponds to the digital signal range and minimizing parasitic capacitance effects, using a binary search method to determine bit values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a conventional capacitance circuit is used in a successive approximation type A/D converter, then the circuit structure is simple, but parasitic capacitances cause conversion errors and unstable full-scale range

Engineering Contradiction:
Improveconversion accuracyVSAvoidcapacitance circuit structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The capacitance circuit is segmented into multiple functional units: a first capacitance unit for holding sampled analog signals, a second capacitance unit for generating comparison voltage signals through reflection, and a third capacitance unit for adjusting the full-scale range. This segmentation allows each unit to be optimized for its specific function, reducing parasitic capacitance effects and improving conversion accuracy while maintaining reasonable structural complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A capacitance value adjustment unit is introduced as an intermediary component between the capacitance circuit and the analog-to-digital conversion process. This unit includes variable capacitance elements that can adjust the total capacitance value to compensate for parasitic capacitances, thereby stabilizing the full-scale range and reducing conversion errors without requiring complete redesign of the capacitance circuit architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the capacitance values are increased to improve full-scale range stability, then parasitic capacitance effects are reduced, but the circuit area and power consumption increase

Engineering Contradiction:
Improvefull-scale range stabilityVSAvoidcircuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The capacitance circuit incorporates variable capacitance elements that can dynamically adjust their capacitance values based on process variations and operating conditions. This dynamic adjustment capability allows the circuit to maintain stable full-scale range without requiring excessive fixed capacitance values, thereby reducing the overall circuit area while ensuring reliability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs parameter changes by introducing adjustable capacitance values that can be tuned to optimize the balance between full-scale range stability and circuit area. The capacitance value adjustment unit modifies the effective capacitance parameters to compensate for parasitic effects without proportionally increasing the physical capacitance element sizes, thus controlling the circuit area occupation.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If process variations are compensated to reduce conversion errors, then measurement precision improves, but device complexity increases

Engineering Contradiction:
Improveconversion accuracyVSAvoidcapacitance adjustment mechanism
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The capacitance value adjustment unit is designed to automatically compensate for process variations without requiring external calibration or complex control mechanisms. The adjustment mechanism uses feedback from the conversion process itself to modify capacitance values, enabling self-correction of process variations and maintaining high conversion accuracy with minimal additional complexity.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces power consumption, minimizes conversion errors, and secures a stable full-scale range, enabling efficient and accurate A/D conversion in successive approximation type A/D converters.

Implementation Method 1

The capacitance circuit includes a first capacitance unit, a second capacitance unit, and a third capacitance unit. The second capacitance unit reflects a signal level of a reference signal in the pair of analog signals sampled by the sampling circuit to generate a pair of voltage signals.

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS10090851B2Successive approximation type analog-to-digital (A/D) converter
Publication Date: 2018.10.02 OLYMPUS CORPORATION(JP)
  • US10090851B2 patent drawing
  • US10090851B2 patent drawing
  • US10090851B2 patent drawing

AI summary

A sampling circuit in a successive approximation type analog-to-digital (A/D) converting device samples a pair of analog signals constituting a differential input signal. A capacitor circuit reflects a signal level of a reference signal in the pair of analog signals through an attenuation capacitance unit and a binary capacitance unit to generate a pair of voltage signals. A comparison circuit compares the pair of voltage signals. A control circuit determines a value of each bit of a digital signal on the basis of the result of the comparison and reflects the value in the reference signal. The attenuation capacitance unit includes a fixed capacitance unit connected between a signal node at which the sampled analog signals are held and a predetermined potential node and a variable capacitance unit connected between the signal node and the predetermined potential node in parallel with the fixed capacitance unit.