Segmented SAR ADC Capacitor Array for Settling Error Tolerance
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Solution Overview
Problem
Existing successive approximation analog-to-digital converters (SAR ADCs) face challenges in tolerating comparison errors from comparators, which limits their settling error tolerance and requires complex calibration logic and multiple capacitors.
Innovation Solution
A SAR ADC design with a capacitor array where M capacitors sum to (2N−1) unit capacitors, allowing sequential switching and comparison, reducing the number of capacitors and simplifying calibration using adders and multiplexers, thereby increasing settling error tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional binary-search SAR ADC is used, then the converter can achieve basic ADC functionality, but the settling error tolerance is limited and comparison errors from comparators cannot be effectively tolerated
Solution Approach 1:
The capacitor array is segmented into multiple sub-capacitor groups, where each group contains sub-capacitors that can be independently switched. This segmentation allows the system to tolerate comparison errors by providing alternative capacitor switching sequences while maintaining the overall binary-weighted capacitance sum, thereby improving settling error tolerance without significantly increasing device complexity.
2Reliability
If non-traditional binary-search methods (sub-radix 2 or redundant radix-2) are used to increase settling error tolerance, then error tolerance capability improves, but the number of capacitors and calibration logic complexity increases
Solution Approach 1:
The patent applies partial action by using sub-capacitors with capacitance values that are fractions of the basic unit capacitor (e.g., 1/2, 1/4, 1/8 of unit capacitor). This allows the capacitor array to achieve enhanced error tolerance through partial capacitor switching operations rather than requiring full redundant capacitor sets, thereby reducing the total number of capacitors needed while maintaining improved settling error tolerance.
3Reliability
If non-traditional binary-search methods are used to improve settling error tolerance, then error tolerance increases, but calibration logic complexity increases
Solution Approach 1:
The patent changes the capacitance parameters of sub-capacitors to specific fractional values (1/2, 1/4, 1/8 of unit capacitor) and configures their switching sequences to correspond to binary-weighted patterns. This parameter optimization allows the calibration logic to be simplified while maintaining enhanced error tolerance, as the fractional capacitance values enable more straightforward calibration algorithms compared to arbitrary capacitor values.
Data Source
AI summary
A successive approximation analog-to-digital converter (SAR ADC) includes a capacitor array and a comparator. The capacitor array has M capacitors which are arranged to perform capacitor switching operations sequentially, wherein a sum of capacitance values of the M capacitors is equal to (2N−1) unit capacitors, M>N, and M and N are both positive integers. The comparator is arranged for comparing an output of the capacitor array and an analog input sequentially.