SAR ADC Capacitor Array for Higher Precision in Less Area
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Solution Overview
Problem
The challenge of implementing a successive approximation register analog-to-digital converter (SAR ADC) with higher precision using a smaller number of capacitors, as the increased number of capacitors leads to larger area and higher cost.
Innovation Solution
A SAR ADC design that utilizes a capacitor array with parallel first and second capacitors, controlled by switch circuits and an SAR logic circuit, which adjusts reference voltages on the capacitor bottom plates with different precisions to achieve higher bit precision without increasing the number of capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of capacitors is increased to achieve higher precision, then the output precision of SAR ADC is improved, but the area and cost of SAR ADC increase
Solution Approach 1:
The capacitor array is divided into two separate arrays: a first capacitor array and a second capacitor array. Each array handles different portions of the conversion process, allowing the system to achieve higher precision without requiring a single large capacitor array. This segmentation enables independent optimization of each array's size and reduces the total area required.
Solution Approach 2:
The patent introduces a time dimension by performing successive approximation conversions in multiple stages. The first capacitor array performs an initial conversion, and the second capacitor array performs a subsequent conversion on the remaining error. This temporal dimension allows precision to be accumulated across time rather than requiring all capacitors to be present simultaneously in space.
2Measurement precision
If the number of capacitors is increased to achieve higher precision, then the output precision of SAR ADC is improved, but the cost of SAR ADC increases
Solution Approach 1:
By segmenting the conversion process into two stages with two capacitor arrays, the patent reduces the total number of capacitors required compared to a single high-precision array. This segmentation lowers manufacturing costs while maintaining or improving precision through the combined output of both arrays.
Solution Approach 2:
The patent uses two capacitor arrays that can be designed with identical or similar structures, allowing for standardized manufacturing processes. This copying approach enables reuse of design templates and manufacturing procedures, reducing development and production costs compared to designing a single complex high-precision array.
3Measurement precision
If more capacitors are used to increase precision, then the precision of SAR ADC output is improved, but the power consumption increases
Solution Approach 1:
The conversion process is segmented into two sequential stages using two capacitor arrays. Each array operates at lower precision requirements individually, reducing the total energy required for charging and discharging operations. The combined effect of both stages achieves high precision without the exponential energy cost of a single high-precision array.
Solution Approach 2:
The patent employs periodic successive approximation conversions, where the first capacitor array performs an initial conversion cycle, followed by the second capacitor array performing a subsequent conversion cycle. This periodic action distributes energy consumption over time and allows for energy recovery and optimization between cycles.
Data Source
AI summary
A successive approximation register digital analog-to-digital converter, and an electronic device. The successive approximation register digital analog-to-digital converter comprises a positive capacitor array, a negative capacitor array, a switching circuit, a comparator and an SAR logic circuit, wherein the SAR logic circuit is configured to control the reference voltages to which the plurality of first capactiros are connected through the plurality of second capacitors are connected through the plurality of groups of second bottom plate switches according to each bit of digital signal outputted by the comparator.