SAR ADC Capacitor Calibration for Better Linearity
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Solution Overview
Problem
Successive approximation analog-to-digital converters (ADCs) are prone to non-linearities due to mismatch in reference elements, leading to differential and integral non-linearities, which cause unwanted spurious tones in AC signal conversions, such as in radar or audio systems.
Innovation Solution
The method involves measuring the weights of DAC reference elements by performing specific sampling operations on a capacitor array, balancing the capacitance coupled to reference voltages during sampling, and using these measurements to correct the ADC output, thereby reducing voltage transients and offsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If device mismatch in capacitor array is present, then ADC architecture remains simple and low power, but non-linearities (DNL and INL) occur causing spurious tones
Solution Approach 1:
The patent applies preliminary calibration before normal ADC operation to measure and correct capacitor weight mismatches. The calibration process measures the actual weight of each capacitor in the DAC array and stores correction values, which are then used during normal operation to compensate for mismatches and eliminate spurious tones.
Solution Approach 2:
The patent changes the operational parameters of the capacitor array by applying different reference voltages (first reference voltage and second reference voltage) to different sets of capacitors during calibration. This allows measurement of individual capacitor weights by comparing outputs when capacitors are connected to different voltage levels, enabling detection and correction of mismatch parameters.
2Measurement precision
If calibration measurements are performed without balancing capacitance, then measurement process is simpler, but voltage transients and offsets increase reducing accuracy
Solution Approach 1:
The patent applies the equipotentiality principle by balancing the total capacitance connected to the first reference voltage against the total capacitance connected to the second reference voltage during calibration sampling. This balancing ensures that the center tap voltage remains stable and free from large transients, enabling accurate measurement of capacitor weights without voltage offsets or noise interference.
Solution Approach 2:
The patent introduces a center tap node as an intermediary element that connects to both reference voltages through balanced capacitance. This center tap serves as a stable reference point that mediates between the two reference voltage sources, allowing accurate measurement while maintaining voltage stability and preventing large transients during the calibration process.
3Measurement precision
If dielectric absorption effects are present, then capacitor performance degrades over time, but no compensation is applied leading to measurement errors
Solution Approach 1:
The patent applies feedback by measuring the actual output voltage during calibration and using this measurement to determine the true weight of each capacitor. The measured weight information is fed back into the system to correct for dielectric absorption effects and other non-ideal behaviors, ensuring accurate calibration measurements are obtained despite the presence of harmful physical effects in the capacitors.
Data Source
AI summary
In accordance with an embodiment, a method for operating a successive approximation ADC comprising a first capacitor array includes measuring a first weight of an MSB-ath bit of the ADC by applying a first reference voltage to first terminals of capacitors of the first capacitor array corresponding to the MSB-ath bit, applying a second reference voltage to first terminals of capacitors of the first capacitor array corresponding to significant bits lower than the MSB-ath bit, applying the first reference voltage to first terminals of a first set of capacitors of the first capacitor array corresponding to significant bits higher than the MSB-ath bit, and applying the second reference voltage to first terminals of a second set of capacitors of the first capacitor array corresponding to the significant bits higher than the MSB-ath bit; subsequently, a weight of a capacitance of the capacitors corresponding to the MSB-ath bit is successively approximated.