SAR ADC Capacitor Correction for Speed and Dynamic Range
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Solution Overview
Problem
Conventional successive-approximation ADCs face increased circuit complexity and reduced operating speed as the number of bits increases, along with deteriorating dynamic range due to manufacturing variations in capacitors.
Innovation Solution
A successive-approximation ADC with a CDAC that includes a main and auxiliary capacitor bank, utilizing a corrected capacitance value designation circuit to supply corrected capacitance values, an offset correction circuit to adjust comparator output, and a multiplexer to select correction values based on feedback, enabling linearity and offset corrections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If correction is performed using an auxiliary capacitor bank and control circuit in conventional successive-approximation ADCs, then manufacturing variations in capacitors are compensated, but circuit complexity and size increase, and operating speed decreases
Solution Approach 1:
The patent merges the auxiliary capacitor bank and main capacitor bank into a unified capacitor array structure. The auxiliary capacitors are integrated alongside the main capacitors, sharing common control signals and readout circuitry, thereby reducing overall circuit complexity while maintaining correction functionality
Solution Approach 2:
The capacitor array is designed to serve multiple functions: the same capacitor bank performs both the primary analog-to-digital conversion and the correction operations. By making the capacitor bank universal, separate dedicated correction circuits are eliminated, reducing device complexity
2Manufacturing precision
If correction is performed using an auxiliary capacitor bank and control circuit in conventional successive-approximation ADCs, then manufacturing variations in capacitors are compensated, but operating speed decreases
Solution Approach 1:
Capacitor correction values are pre-calculated and stored in lookup tables during manufacturing or initialization. During normal operation, the system performs rapid table lookups based on measured capacitor values, avoiding time-consuming real-time correction calculations and maintaining high operating speed
Solution Approach 2:
The patent replaces complex real-time correction circuitry with a digital lookup table-based correction system. This substitution of analog correction mechanisms with digital processing accelerates the correction process, maintaining high operating speed while achieving accurate compensation
3Measurement precision
If the number of supported bits increases in conventional successive-approximation ADCs, then resolution improves, but circuit size increases and operating speed decreases
Solution Approach 1:
The capacitor bank is segmented into main capacitors and auxiliary capacitors with distinct functional roles. This segmentation allows the auxiliary capacitors to provide correction for manufacturing variations across all bit resolutions without proportionally increasing the main conversion capacitor array size, enabling high-resolution conversion with controlled area growth
4Measurement precision
If the number of supported bits increases in conventional successive-approximation ADCs, then resolution improves, but operating speed decreases
Solution Approach 1:
Correction values for all possible capacitor variations are pre-calculated and stored in lookup tables during manufacturing. During operation, regardless of bit resolution, the system performs rapid table lookups rather than real-time correction calculations, maintaining constant operating speed even as resolution increases
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution suppresses circuit size increase and speeds up operations while improving accuracy and maintaining dynamic range, even with increased bit support.
Implementation Method 1
a successive-approximation ADC using a capacitance redistribution method
Data Source
AI summary
The present invention aims to suppress an increase in the size of a circuit configuration and achieve speed-up. The present invention is a successive-approximation ADC including: a CDAC consisting of a main capacitor bank consisting of a plurality of first capacitors and an auxiliary capacitor bank including a plurality of second capacitors to supply a corrected capacitance value to the first capacitors, a comparator configured to output a bit signal based on a capacitance redistribution signal output according to capacitance redistribution by the CDAC in response to an analog input signal, a logic circuit configured to output a digital output signal based on the bit signal, and a corrected capacitance value designation circuit configured to output a correction designation value that designates a corrected capacitance value to be supplied to the first capacitors. The corrected capacitance value designation circuit holds in advance two correction designation values before 1 bit as pre-correction designation values, selects one of the pre-correction designation values according to the bit signal from the comparator, and calculates two most recent correction designation values based on the bit signal.