SAR ADC Capacitor Layout for Low Top-Plate Parasitic Capacitance

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Solution Overview

Problem

Conventional metal-oxide-metal capacitors in successive approximation register (SAR) analog-to-digital converters (ADCs) face increasing parasitic capacitance issues due to shrinking feature sizes, which degrade the full-scale voltage range and performance.

Innovation Solution

A low parasitic capacitance architecture is implemented by shielding the top plate of the capacitors with the structures of the bottom plate, converting undesirable parasitic capacitance into effective capacitance between the top and bottom plates, using a conductive material like copper for the bottom plate shielding structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If feature size of metal layers is shrunk to reduce capacitor area, then area of capacitor is reduced, but parasitic capacitance on metal connection nodes becomes more significant

Engineering Contradiction:

Improvecapacitor areaVSAvoidparasitic capacitance

Core Design Contradiction:

Area of moving objectVSObject-affected harmful factors

Solution Approach 1:

The patent converts the harmful parasitic capacitance on the top plate into beneficial effective capacitance by connecting it in parallel with the bottom plate capacitance. The shielding structure captures the parasitic capacitance that would otherwise be lost and adds it to the functional capacitance, thereby improving the effective capacitance without increasing the physical area.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent introduces a shielding structure as an intermediary element between the top plate and the surrounding environment. This shielding structure acts as a mediator that captures and redirects the parasitic capacitance fields, converting them into useful capacitance through the connection to the bottom plate.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Speed

If conventional top plate sampling architecture is used, then high speed operation is achieved, but parasitic capacitance degrades full-scale voltage range and performance

Engineering Contradiction:

Improveoperation speedVSAvoidperformance

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent converts the harmful parasitic capacitance that limits full-scale voltage range into beneficial effective capacitance. By shielding the top plate and connecting the parasitic capacitance to the bottom plate, the patent improves both the voltage range and performance while maintaining the high-speed operation enabled by the top plate sampling architecture.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Speed

If unit capacitor capacitance is reduced for high speed, then speed is improved, but mismatch becomes more significant

Engineering Contradiction:

Improveconversion speedVSAvoidcapacitor matching

Core Design Contradiction:

SpeedVSManufacturing precision

Solution Approach 1:

The patent merges the parasitic capacitance with the functional capacitance by connecting them in parallel through the shielding structure. This combination increases the total effective capacitance, allowing for larger unit capacitor values that improve matching precision while still maintaining high-speed operation.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces parasitic capacitance on the top plate node, maintaining low unit capacitor mismatch and enhancing the full-scale voltage range, thereby improving the performance of SAR ADCs.

Implementation Method 1

parasitic capacitance on metal connection nodes become more significant as compared with the capacitance of the MOM capacitor

Methodology Applied

Scientific EffectParasitic capacitance: Parasitic Capacitance

Data Source

PatentUS12580581B2Low parasitic capacitance architecture for successive approximation register analog-to-digital converters

Publication Date: 2026.03.17 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

A unit capacitor for a switched-capacitor digital-to-analog converter is provided. An apparatus includes a first plate formed of a conductive material, wherein the first plate comprises one or more first fingers, wherein each respective first finger of the one or more first fingers has an elongated structure extending longitudinally in a first direction. The apparatus further includes a second plate formed of the conductive material, wherein the second plate comprises two or more second fingers, wherein each respective second finger of the two or more second fingers has an elongated structure extending in a second direction. Each first finger of the one or more first fingers is disposed between two adjacent second fingers of the two or more second fingers.