SAR ADC Attenuation Capacitor Calibration for PVT-Stable Linearity
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Solution Overview
Problem
Existing SAR ADC technologies face challenges in accurately calibrating the attenuation capacitor, which is critical for maintaining low power consumption and small form factor, especially under varying process, voltage, and temperature conditions, leading to performance issues like differential nonlinearity (DNL) and accuracy errors.
Innovation Solution
The introduction of a correction capacitor with a fixed capacitance value coupled to the attenuation capacitor, along with a variable voltage reference, allows for precise calibration by adjusting the charge on the correction capacitor to compensate for capacitance value errors, using a calibration digital-to-analog converter (cDAC) to stabilize the capacitance across a wide range of conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a varactor (voltage variable capacitor) is used to correct parasitic capacitance variations, then the attenuation capacitor can be adjusted for process and temperature variations, but the varactor introduces its own variable parasitic capacitance that causes bigger capacitance variation across PVT conditions
Solution Approach 1:
The patent creates a copy of the attenuation capacitor's parasitic capacitance characteristics using a bottom-plate capacitor and replicates the PVT variations through a bottom-plate replica. This replica captures the same parasitic effects without introducing additional variable parasitic capacitance, allowing accurate compensation of the original capacitor's variations.
Solution Approach 2:
The patent introduces a bottom-plate replica capacitor as an intermediary that mimics the parasitic capacitance variations of the top-plate capacitor. This replica serves as a mediator to capture and represent the PVT variations without adding its own variable parasitic effects, enabling accurate tracking and compensation.
2Manufacturing precision
If silicon iteration based on measurement data is used to correct parasitic capacitance value, then the attenuation capacitor can be manufactured with better than 0.25 percent accuracy, but it requires multiple fabrication iterations and is impossible to get the correct capacitance needed the first time
Solution Approach 1:
The patent performs preliminary characterization of parasitic capacitance effects during the design phase by creating a bottom-plate replica that captures these effects. This preliminary action allows the system to pre-compensate for known parasitic variations without requiring post-fabrication silicon iteration, achieving high precision in a single fabrication run.
Solution Approach 2:
The patent creates a copy of the parasitic capacitance effects using a bottom-plate replica capacitor. This copy allows the design to account for and compensate parasitic variations before fabrication, eliminating the need for iterative silicon corrections and reducing fabrication complexity.
3Ease of manufacture
If the attenuation capacitor depends on parasitic capacitance in an integrated circuit silicon die, then it can be fabricated in standard CMOS process, but the parasitic capacitance causes accuracy errors and requires tight tolerance manufacturing
Solution Approach 1:
The patent converts the harmful effect of parasitic capacitance into a beneficial measurement tool. By creating a bottom-plate replica that intentionally reproduces the same parasitic effects, the previously harmful parasitic capacitance becomes a useful indicator for characterizing and compensating accuracy errors, enabling high precision without sacrificing ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides robust calibration of the attenuation capacitor, reducing DNL errors and maintaining stability across process, voltage, and temperature variations, ensuring accurate SAR ADC operation with minimal performance variation.
Implementation Method 1
a correction capacitor (Ccal) having a fixed capacitance value, wherein the correction capacitor (Ccal) is coupled to the attenuation capacitor (Ca); and a variable voltage reference (VREFM); wherein a voltage from the variable voltage reference (VREFM) is adjusted to vary a charge on the correction capacitor (Ccal) for compensating a capacitance value error of the attenuation capacitor (Ca)
Data Source
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AI summary
A fixed capacitor is coupled between a top plate of an attenuation capacitor and a variable voltage reference. The error in the attenuation capacitor may be calibrated out with the variable voltage reference and the fixed correction capacitor. The variable voltage reference varies the charge on the attenuation capacitor and thereby compensates for error(s) therein. A calibration digital-to-analog converter may be used in conjunction with or substituted for the variable voltage reference, and may be programmed for different charge compensation values from the SAR logic during an iterative SAR DAC capacitive switching process.