SAR ADC Capacitor Bank Mixing for Lower-Power RF Receivers
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Solution Overview
Problem
Existing radio frequency receivers face challenges in down-conversion and analog-to-digital conversion, leading to high complexity, power consumption, and inefficient use of ADC resources.
Innovation Solution
A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is combined with the harmonic rejection mixer (HRM) function, leveraging the capacitive digital-to-analog converter (C-DAC) for both ADC and HRM functionality, and incorporating noise shaping to reduce resolution requirements and increase accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If down-conversion is performed in the digital domain, then the ADC can operate at lower frequencies, but the ADC requires relatively large bandwidth which entails high ADC complexity and high power consumption
Solution Approach 1:
The patent combines the harmonic rejection mixer (HRM) functionality with the SAR ADC into a single integrated circuit. The capacitor bank used for digital-to-analog conversion in the SAR ADC is also utilized to perform the mixing operation, merging two separate functions into one unified structure. This integration directly reduces ADC complexity by eliminating the need for a separate down-conversion stage while maintaining conversion accuracy.
Solution Approach 2:
The capacitor bank in the SAR ADC is designed to serve dual purposes: performing digital-to-analog conversion for the ADC function and simultaneously acting as the mixing element for down-conversion. This multi-functionality allows the same hardware resources to handle both signal conversion and frequency translation, reducing overall system complexity and power consumption.
2Use of energy by moving object
If down-conversion is performed in the analog domain using a harmonic rejection mixer, then the ADC bandwidth requirement is reduced, but the down-conversion complexity and power consumption increase
Solution Approach 1:
The patent merges the HRM and SAR ADC into a single integrated circuit where the same capacitor bank performs both mixing and digital-to-analog conversion. This eliminates the need for a separate analog down-conversion stage, thereby reducing down-conversion complexity while maintaining power efficiency.
Solution Approach 2:
The patent replaces the traditional analog mixing mechanism with a digital-domain approach using the SAR ADC's capacitor bank. Instead of using complex analog circuitry for harmonic rejection mixing, the invention uses the existing digital-to-analog conversion infrastructure to perform the mixing operation, simplifying the overall system.
3Productivity
If a traditional SAR ADC is used without integrated mixing functionality, then the ADC design is simpler, but the ADC resources are used inefficiently and additional down-conversion hardware is required
Solution Approach 1:
The capacitor bank is designed to perform multiple functions: digital-to-analog conversion for the SAR ADC and mixing for down-conversion. This multi-functionality maximizes the utilization of ADC resources, eliminating idle hardware and improving overall system efficiency without significantly increasing complexity.
Solution Approach 2:
The SAR ADC's own capacitor bank serves the additional function of performing mixing operations. Instead of requiring external dedicated mixing hardware, the ADC system uses its internal resources to accomplish the down-conversion task, making the system more self-sufficient and resource-efficient.
Data Source
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AI summary
A successive approximation register analog-to-digital converter (SAR ADC) is disclosed, which is configured to receive an analog input signal and provide a digital output signal. The SAR ADC comprises a capacitor bank for successively providing a plurality of signal levels based on a sample value of the analog input signal, wherein each signal level of the plurality is an indicator for a corresponding bit in a corresponding sample of the digital output signal. Furthermore, the SAR ADC comprises controlling circuitry configured to cause the capacitor bank to provide the plurality of signal levels representing a dynamically scaled version of the sample value of the analog input signal.In some embodiments, a respective selector of each capacitor of the capacitor bank is controlled to charge the capacitor using either the sample value of the analog input signal or the sample value of an opposed version of the analog input signal. The setting of the respective selectors corresponds to a digital representation of a scaling value (e.g., a sample value of an oscillator signal) for the dynamically scaled version of the sample value of the analog input signal. Corresponding method, receiver, and wireless communication device are also disclosed..